Abstract: A packet processing integrated circuit chip includes a plurality of input ports configured to receive packets from respective external sources and a plurality of output ports configured to transmit packets to respective external recipients. The chip further includes a packet processor configurable to process the received packets to generate new output packets with new payloads according to selected ones of a plurality of packet processing scenarios and to convey the new output packets to the output ports. Timing of each packet processing scenario is controlled responsive to received packet accumulation for the packet processing scenario. The chip may further include a packet switching fabric configured to route selected packets from the input ports to selected ones of the output ports without payload modification.