Patents by Inventor A Man Zheng
A Man Zheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942784Abstract: The present invention discloses a method and device for formulating a coordinated action strategy of SSTS and DVR for voltage sag mitigation. The influence of voltage sag on a whole industrial process of a sensitive user is analyzed, and the sensitive loads of SSTS and DVR which satisfy a governance need are grouped; a practical governance scenario of installing a plurality of DVR is considered to install a minimum-capacity DVR to realize a target of a minimum interruption probability of the whole industrial process of the user; an optimal coordinated governance solution of SSTS and DVR based on sensitive load grouping is proposed; a classification result is obtained for duration time at a time when a voltage sag event occurs through a decision tree constructed based on historical data.Type: GrantFiled: June 24, 2022Date of Patent: March 26, 2024Assignee: Sichuan UniversityInventors: Ying Wang, Man Wang, Xianyong Xiao, Wenxi Hu, Yang Wang, Zixuan Zheng, Yunzhu Chen
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Publication number: 20230084008Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.Type: ApplicationFiled: September 13, 2021Publication date: March 16, 2023Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
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Publication number: 20230083030Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.Type: ApplicationFiled: November 10, 2022Publication date: March 16, 2023Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
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Patent number: 11145666Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.Type: GrantFiled: May 28, 2020Date of Patent: October 12, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
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Patent number: 11101276Abstract: Embodiments of semiconductor structures including word line contact structures for three-dimensional memory devices and fabrication methods for forming word line contact structures are disclosed. The semiconductor structures include a staircase structure having a plurality of steps, and each step includes a conductive layer disposed over a dielectric layer. The semiconductor structures further include a barrier layer disposed over a portion of the conductive layer of each step. The semiconductor structures also include an etch-stop layer disposed on the barrier layer and an insulating layer disposed on the etch-stop layer. The semiconductor structures also include a plurality of conductive structures formed in the insulating layer and each conductive structure is formed on the conductive layer of each step.Type: GrantFiled: May 1, 2020Date of Patent: August 24, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Jifeng Zhu, Zhenyu Lu, Jun Chen, Si Ping Hu, Xiaowang Dai, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
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Publication number: 20200295019Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads. where each landing pad is disposed over another portion of the second material layer of a respective layer stack.Type: ApplicationFiled: May 28, 2020Publication date: September 17, 2020Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu LU, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
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Publication number: 20200258837Abstract: Embodiments of semiconductor structures including word line contact structures for three-dimensional memory devices and fabrication methods for forming word line contact structures are disclosed. The semiconductor structures include a staircase structure having a plurality of steps, and each step includes a conductive layer disposed over a dielectric layer. The semiconductor structures further include a barrier layer disposed over a portion of the conductive layer of each step. The semiconductor structures also include an etch-stop layer disposed on the barrier layer and an insulating layer disposed on the etch-stop layer. The semiconductor structures also include a plurality of conductive structures formed in the insulating layer and each conductive structure is formed on the conductive layer of each step.Type: ApplicationFiled: May 1, 2020Publication date: August 13, 2020Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Jifeng ZHU, Zhenyu LU, Jun CHEN, Si Ping HU, Xiaowang DAI, Lan YAO, Li Hong XIAO, A Man ZHENG, Kun BAO, Haohao YANG
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Patent number: 10680003Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.Type: GrantFiled: September 10, 2018Date of Patent: June 9, 2020Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
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Patent number: 10672711Abstract: Embodiments of semiconductor structures including word line contact structures for three-dimensional memory devices and fabrication methods for forming word line contact structures are disclosed. The semiconductor structures include a staircase structure having a plurality of steps, and each step includes a conductive layer disposed over a dielectric layer. The semiconductor structures further include a barrier layer disposed over a portion of the conductive layer of each step. The semiconductor structures also include an etch-stop layer disposed on the barrier layer and an insulating layer disposed on the etch-stop layer. The semiconductor structures also include a plurality of conductive structures formed in the insulating layer and each conductive structure is formed on the conductive layer of each step.Type: GrantFiled: September 10, 2018Date of Patent: June 2, 2020Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Jifeng Zhu, Zhenyu Lu, Jun Chen, Si Ping Hu, Xiaowang Dai, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
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Publication number: 20190096810Abstract: Embodiments of semiconductor structures including word line contact structures for three-dimensional memory devices and fabrication methods for forming word line contact structures are disclosed. The semiconductor structures include a staircase structure having a plurality of steps, and each step includes a conductive layer disposed over a dielectric layer. The semiconductor structures further include a barrier layer disposed over a portion of the conductive layer of each step. The semiconductor structures also include an etch-stop layer disposed on the barrier layer and an insulating layer disposed on the etch-stop layer. The semiconductor structures also include a plurality of conductive structures formed in the insulating layer and each conductive structure is formed on the conductive layer of each step.Type: ApplicationFiled: September 10, 2018Publication date: March 28, 2019Applicant: Yangtze Technologies Co., Ltd.Inventors: Jifeng ZHU, Zhenyu LU, Jun CHEN, Si Ping HU, Xiaowang DAI, Lan YAO, Li Hong XIAO, A Man ZHENG, Kun BAO, Haohao YANG
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Publication number: 20190081070Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.Type: ApplicationFiled: September 10, 2018Publication date: March 14, 2019Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu LU, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang