Abstract: A system and method are provided for compensating for output error in a sigma delta circuit. The system includes an input for receiving an input signal and an output configured to output a output signal. The system further includes a summation component configured to add a first error voltage value, which is derived from an output signal, to an incoming input signal, and a subtraction component configured to subtract a second error voltage value, where the second error voltage value is derived from the adding of a first error voltage value to an incoming input signal.

Abstract: A high quality DAC is provided for a lower cost (including the layout size of the circuit on an audio chip) of high end DACs. The DAC includes a first circuit configured to remove even harmonics from a sigma delta circuit, and a second circuit configured to remove odd harmonics.

Abstract: A signal processor has a plurality of channels, each channel configured to receive an input signal stream, to reduce the signal to a direct current signal and to process the signal according to the stream signal. Each channel also has a plurality of low pass filters configured to filter in-phase and quadrature-phase modulator outputs with a first low pass filter and to filter a reference quadrature signals, and a gain control configured to re-modulate gain adjusted output signals with the filtered quadrature signals. The processor further includes an inverter to invert the in-phase filtered reference signal and means to multiply the quadrature gain adjusted output signal.

Abstract: An improved segmented analog to digital converter is provided, configured with a novel method of compensating current flow in secondary or successive segmented elements. In operation, dual current devices initially load, then subsequently unload a cascade of resistor networks connected to the secondary or successive voltage segmenting elements, preventing the perturbation of precise operation of the primary or preceding elements. In contrast to conventional approaches, the improved converter obviates the need for a buffer or amplifier to isolate the secondary and successive voltage segmenting elements from the primary or preceding elements.

Abstract: A differential input flash analog-to-digital converter in which an array of comparators is connected to compare reference signals within a parabolic distribution of such signals generated by the application of a differential input signal across an impedance network. Preferably, the comparator array comprises at least two pluralities of comparators, the first plurality of comparators comparing pairs of reference nodes separated by a first step size, and the second plurality of comparators comparing pairs of reference nodes separated by a second step size. Even more preferably, the comparator array further comprises a third plurality of comparators comparing pairs of reference nodes separated by a third step size, but only where necessary to maximize the available comparison range of the converter. The flash converter according to the invention provides increased gain from input without accumulation of comparator input currents and without sacrificing the number of actual comparisons of reference signals.

Abstract: An electronic device is provided such as an amplifier, for example, having improved gain and transconductance and low output impedance. The device includes a primary amplifier configured to carry an operating load. The primary amplifier includes an input for receiving an input signal, and an output for outputting an output signal, and operates having a variable output, as it carries an operational load. The device further includes a secondary amplifier configured to operate at a fixed operating condition, not burdened by carrying an operational load, and includes a secondary input configured to receive the input signal, wherein the secondary amplifier is configured to define the input voltage. The device is configured to detect a difference in operating current between the primary and secondary. amplifiers, and to compensate for any operational load that may be applied to the primary amplifier during operation.

Abstract: A sigma delta circuit is provided having a sigma delta modulator configured to operate according to a first clock signal and a quantizer connected to the sigma delta modulator, where the quantizer is configured to operate according to a second clock signal. In operation, if a small amplitude signal is received by the sigma delta circuit, the circuit is configured to operate at a fixed output frequency. When a large amplitude signal is received, the circuit is configured to adjust to a different frequency to accommodate the larger signal. The second clock signal may be a variable clock signal, where the quantizer operates according to a variable clock signal in order to adjust to different input signals.

Abstract: A device is provided having at least two capacitive elements configured to retain a charge, and an interconnection of active devices between the capacitive elements. The active devices are configured to operate upon a transient charge flow as a current when in operation. The charge flow is partitioned into at least two capacitors according to the input voltage difference acting as a controlling parameter.

Abstract: The invention is directed to a bi-quad filter circuit configured with sigma-delta devices that operate as binary rate multipliers (BRMs). Unlike conventional bi-quad filter circuits, the invention provides a bi-quad filter configured with a single-bit BRM. In another embodiment, the invention further provides a bi-quad filter configured with multiple-bit BRMs.

Abstract: The invention provides a frequency locked loop and related method that enables the conversion of a signal frequency with improved stability. A frequency locked loop embodying the invention includes an input for receiving an input signal and an output for outputting an output signal having a different frequency than the input. A frequency detector is configured to receive the first factored input from the primary channel and the second factored input from the secondary channel, to calculate the difference between the first factored input and the second factored input and to produce an output based on the difference between the two factored inputs. A voltage controlled oscillator is configured to receive the output from the frequency detector, and to produce an output signal. The voltage controlled oscillator ultimately sets the output frequency based on the output of frequency detector.

Abstract: An analog-to-digital converter in which each of a plurality of comparators is, in a successive approximation manner, selectively enabled or disabled and the outputs from those comparators summed together to produce a digital signal therefrom. By weighting and mixing outputs of adjacent comparators in proportions calculated to provide an interpolated output of a virtual comparator between the actual comparators, many such virtual comparators can be created without the need for additional fixed hardware elements in the converter. By doing so, the converter is able to produce a digital output having n bits using only N actual hardware elements for comparing signals, where N<2n−1. Each of the plurality of comparators in the converter has an input for an enabling signal, which enabling signal can be manipulated to enable or disable individual comparators and to modify their outputs. A method for converting an analog input signal into a digital signal using such a converter.

Abstract: The invention provides a method and apparatus for performing a voltage to current conversion. In particular, the invention provides a voltage to current converter configured to vary its transconductance (Gm). Such a converter is configured to receive a voltage input signal combined with a reference voltage signal to be converted to a current output. Optionally, the reference voltage signal may be provided by a parabolic impedance network that includes a bank of resistors and a plurality of corresponding current sources. Each current source corresponds to each node between two resistors, and may be varied in order to program changes in the comparator's Gm. Each resistor and corresponding current source is configured to create an individual reference voltage reference having a value that occurs in a parabolic manner in relation to other voltage references occurring across the impedance network.

Abstract: An analog-to-digital converter in which each of a plurality of comparators is, in a successive approximation manner, selectively enabled or disabled and the outputs from those comparators summed together to produce a digital signal therefrom. By weighting and mixing outputs of adjacent comparators in proportions calculated to provide an interpolated output of a virtual comparator between the actual comparators, many such virtual comparators can be created without the need for additional fixed hardware elements in the converter. By doing so, the converter is able to produce a digital output having n bits using only N actual hardware elements for comparing signals, where N<2n−1. Each of the plurality of comparators in the converter has an input for an enabling signal, which enabling signal can be manipulated to enable or disable individual comparators and to modify their outputs. A method for converting an analog input signal into a digital signal using such a converter.

Abstract: A differential input flash analog-to-digital converter in which an array of comparators is connected to compare reference signals within a parabolic distribution of such signals generated by the application of a differential input signal across an impedance network. Preferably, the comparator array comprises at least two pluralities of comparators, the first plurality of comparators comparing pairs of reference nodes separated by a first step size, and the second plurality of comparators comparing pairs of reference nodes separated by a second step size. Even more preferably, the comparator array further comprises a third plurality of comparators comparing pairs of reference nodes separated by a third step size, but only where necessary to maximize the available comparison range of the converter. The flash converter according to the invention provides increased gain from input without accumulation of comparator input currents and without sacrificing the number of actual comparisons of reference signals.

Abstract: A differential input flash analog-to-digital converter in which an array of comparators is connected to compare reference signals within a parabolic distribution of such signals generated by the application of a differential input signal across an impedance network. Preferably, the comparator array comprises at least two pluralities of comparators, the first plurality of comparators comparing pairs of reference nodes separated by a first step size, and the second plurality of comparators comparing pairs of reference nodes separated by a second step size. Even more preferably, the comparator array further comprises a third plurality of comparators comparing pairs of reference nodes separated by a third step size, but only where necessary to maximize the available comparison range of the converter. The flash converter according to the invention provides increased gain from input without accumulation of comparator input currents and without sacrificing the number of actual comparisons of reference signals.

Abstract: A differential input flash analog-to-digital converter in which an array of comparators is connected to compare reference signals within a parabolic distribution of such signals generated by the application of a differential input signal across an impedance network. Preferably, the comparator array comprises at least two pluralities of comparators, the first plurality of comparators comparing pairs of reference nodes separated by a first step size, and the second plurality of comparators comparing pairs of reference nodes separated by a second step size. Even more preferably, the comparator array further comprises a third plurality of comparators comparing pairs of reference nodes separated by a third step size, but only where necessary to maximize the available comparison range of the converter. The flash converter according to the invention provides increased gain from input without accumulation of comparator input currents and without sacrificing the number of actual comparisons of reference signals.

Abstract: An electronic filter operates as a correlator that provides a discrete approximation of an analog signal. The analog to digital conversion is integrated directly approximation calculation. An array of sample and hold circuits or single bit comparators provide outputs to a series of multipliers, the other input of which is a coefficient value of a Fourier series approximation of the desired frequency response. Each of the sample and hold circuits samples sequentially in time and holds its sample until the next cycle. Thus the sample point rotates in time through the array and each new sample is multiplied by a different coefficient. The output of the multipliers is summed for evaluation.

Abstract: A charge sensitive amplifier with high common mode signal rejection includes an NPN bipolar junction transistor (BJT) and a P-channel metal oxide semiconductor field effect transistor (MOSFET) connected in a totem pole circuit configuration. The BJT base terminal receives a dc reference voltage, the MOSFET gate terminal receives the incoming data signal, the MOSFET drain terminal is grounded and the BJT collector terminal provides the output voltage signal and is biased by the power supply through a resistive circuit element. The MOSFET operates as a source follower amplifier with the transconductance of the BJT serving as the load at the source terminal, while the BJT operates as a common emitter amplifier with the transconductance of the MOSFET providing emitter degeneration. The signal gains of such source follower and common emitter amplifiers are substantially equal and of opposite polarities. Therefore, any common mode signal components due to common mode input signals present at the input terminals (i.

Abstract: A signal sampling circuit for performing correlated double sampling (CDS) of an input signal with a pipelined sample and hold architecture includes a time multiplexed integrating amplifier circuit in which the output circuit is a pipelined sample and hold circuit which provides time multiplexed input signal samples and the feedback integration capacitor is discharged between samples. At all times, one of the channels of the pipelined sample and hold circuit is providing one of the time multiplexed input signal samples while the other channel continues tracking the input signal. The feedback integration capacitor acts as a clamp to null out residual reset noise received as part of the input signal to be sampled. Hence, with the exception of that very brief period of time necessary for switching between the two pipelined sample and hold circuit channels, one of the two pipelined sample and hold circuit channels is always available for signal acquisition.

Abstract: A current mode analog signal multiplexor includes multiple input multiplexed differential amplifiers, and an output differential current amplifier. An input multiplex control signal selects and enables one of the input multiplexed differential amplifiers for buffering and steering the input signal current to one side of the output differential current amplifier. The reference amplifier drives the other side of the output differential current amplifier. The output node of the output differential current amplifier remains at a substantially constant voltage potential while providing an output current which varies in relation to the selected input signal.