Patents by Inventor A. N. Sreeram
A. N. Sreeram has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210162704Abstract: Fabricate a panel (5) by building a sacrificial relief (10) by an additive process of multilayer deposition, applying a facade layer (20,30) over the sacrificial relief so as to conform to the contour of the sacrificial relief, depositing a foamable composition (40, 50, 60) over the facade layer.Type: ApplicationFiled: May 7, 2018Publication date: June 3, 2021Inventors: Attiganal N. Sreeram, Daniel S. Woodman, Michael J. Radler, Gary D. Parsons, Robert Baumann, Jai Venkatesan, Mark A. Barger, Stéphane Costeux, Michael H. Mazor, Richard Cesaretti
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Publication number: 20100243046Abstract: Chalcogenide based photovoltaic devices cells with good resistance to environmental elements can be formed by direct low temperature deposition of inorganic barrier layers onto the film. A unique multilayer barrier can be formed in a single step when reactive sputtering of the silicon nitride onto an inorganic oxide top layer of the PV device.Type: ApplicationFiled: March 23, 2010Publication date: September 30, 2010Inventors: Marty W. Degroot, Rebekah K. Feist, Mark T. Bernius, William F. Banholzer, Chung-Hei Yeung, Attiganal N. Sreeram, Robert P. Haley, JR.
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Patent number: 7778038Abstract: The present invention relates to a power core comprising: at least one embedded surface mount technology (SMT) discrete chip capacitor layer comprising at least one embedded SMT discrete chip capacitor; and at least one planar capacitor laminate; wherein at least one planar capacitor laminate serves as a low inductance path to supply a charge to at least one embedded SMT discrete chip capacitor; and wherein said embedded SMT discrete chip capacitor is connected in parallel to said planar capacitor laminate.Type: GrantFiled: November 30, 2005Date of Patent: August 17, 2010Assignee: E.I. du Pont de Nemours and CompanyInventors: David Ross McGregor, Daniel Irwin Amey, Jr., Sounak Banerji, William J. Borland, Karl Hartmann Dietz, Attiganal N. Sreeram
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Patent number: 7663242Abstract: A solder preform having multiple layers including a solder layer filled with additives interposed between two unfilled layers for improved wettability. A solder preform having a sphere which contains a solder material filled with additives, and an unfilled surface layer for improved wettability. A thermal interface material having a bonding component and an additive component which is a CTE modifying component and/or a thermal conductivity enhancement component. Active solders containing intrinsic oxygen getters.Type: GrantFiled: March 6, 2007Date of Patent: February 16, 2010Inventors: Brian G. Lewis, Bawa Singh, John P. Laughlin, David V. Kyaw, Anthony E. Ingham, Attiganal N. Sreeram, Leszek Hozer, Michael J. Liberatore, Gerard R. Minogue
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Patent number: 7613007Abstract: The present invention relates to a device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor; and at least one planar capacitor laminate; wherein said planar capacitor laminate serves as a low inductance path to supply a charge to said at least one embedded singulated capacitor; and wherein said at least one embedded singulated capacitor is connected in parallel to at least one of the said planar capacitor laminates; and wherein said power core is interconnected to at least one signal layer.Type: GrantFiled: November 30, 2005Date of Patent: November 3, 2009Assignee: E. I. du Pont de Nemours and CompanyInventors: Daniel Irwin Amey, Jr., Sounak Banerji, William J. Borland, Karl Hartmann Dietz, David Ross McGregor, Attiganal N. Sreeram
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Publication number: 20070284731Abstract: The mounting structure of a power device is simplified so as to reduce cost while achieving improvements in heat dissipation and reliability. A power module 100 is comprised of a metal wiring board 13, a power device 11 disposed on an upper surface of the metal wiring board 13 via a solder layer 12, a metal heat dissipating plate 15 disposed on a lower surface of the metal wiring board 13, and a heat sink 19 disposed on a lower surface of the metal heat dissipating plate 15. A resin-based insulating layer 14 is disposed between any desired two of the aforementioned layers.Type: ApplicationFiled: March 15, 2007Publication date: December 13, 2007Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, E.I. DU PONT DE NEMOURS AND COMPANYInventors: Takashi Atsumi, Junzo Ukai, Kenji Eto, Kenji Nakamura, Sezto Daiza, Paul Arthur Meloni, Attignal N. Sreeram, Kurt Douglas Roberts, David Leroy Sutton
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Patent number: 7187083Abstract: A solder preform having multiple layers including a solder layer filled with additives interposed between two unfilled layers for improved wettability. A solder preform having a sphere which contains a solder material filled with additives, and an unfilled surface layer for improved wettability. A thermal interface material having a bonding component and an additive component which is a CTE modifying component and/or a thermal conductivity enhancement component. Active solders containing intrinsic oxygen getters.Type: GrantFiled: November 25, 2003Date of Patent: March 6, 2007Assignee: Fry's Metals, Inc.Inventors: Brian G. Lewis, Bawa Singh, John P. Laughlin, David V. Kyaw, Anthony E. Ingham, Attiganal N. Sreeram, Leszek Hozer, Michael J. Liberatore, Gerard R. Minogue
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Publication number: 20040200879Abstract: A solder preform having multiple layers including a solder layer filled with additives interposed between two unfilled layers for improved wettability. A solder preform having a sphere which contains a solder material filled with additives, and an unfilled surface layer for improved wettability. A thermal interface material having a bonding component and an additive component which is a CTE modifying component and/or a thermal conductivity enhancement component. Active solders containing intrinsic oxygen getters.Type: ApplicationFiled: November 25, 2003Publication date: October 14, 2004Applicant: Fry's Metals, Inc.Inventors: Brian G. Lewis, Bawa Singh, John P. Laughlin, David V. Kyaw, Anthony E. Ingham, Attiganal N. Sreeram, Leszek Hozer, Michael J. Liberatore, Gerard R. Minogue
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Patent number: 6653741Abstract: A thermal interface material for use in electronic packaging, the thermal interface material comprises a solder with relatively high heat flow characteristics and a CTE modifying component to reduce or prevent damage due to thermal cycling. The thermal interface material comprises an active solder that contains indium and an intrinsic oxygen getter selected from the group consisting of alkali metals, alkaline-earth metals, refractory metals, rare earth metals and zinc and mixtures and alloys thereof. Lastly, damage due to an electronic package due to thermal cycling stress is reduced by using an insert in a lid of an electronic device package wherein the insert has a coefficient of thermal expansion that is between about that of the lid and about that of a semiconductor substrate.Type: GrantFiled: May 20, 2002Date of Patent: November 25, 2003Assignee: Fry's Metals, Inc.Inventors: Attiganal N. Sreeram, Brian Lewis, Leszek Hozer, Michael James Liberatore, Gerard Minogue
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Publication number: 20020175403Abstract: A thermal interface material for use in electronic packaging, the thermal interface material comprises a solder with relatively high heat flow characteristics and a CTE modifying component to reduce or prevent damage due to thermal cycling. The thermal interface material comprises an active solder that contains indium and an intrinsic oxygen getter selected from the group consisting of alkali metals, alkaline-earth metals, refractory metals, rare earth metals and zinc and mixtures and alloys thereof. Lastly, damage due to an electronic package due to thermal cycling stress is reduced by using an insert in a lid of an electronic device package wherein the insert has a coefficient of thermal expansion that is between about that of the lid and about that of a semiconductor substrate.Type: ApplicationFiled: May 20, 2002Publication date: November 28, 2002Applicant: Fry's Metals, Inc.Inventors: A. N. Sreeram, Brian Lewis, Leszek Hozer, Michael James Liberatore, Gerard Minogue