Abstract: A low-power pipelined data processor (20) includes a branch prediction mechanism for speculatively placing branch target instructions into the fetch, decode, dispatch, and execute pipeline when a branch is predicted to be taken. To save power the data processor (20) selectively disables one or more pipeline resources (24) associated with placing the branch target instructions into the pipeline according to the strength of the prediction. If the prediction is weakly not taken, the data processor (20) enables the pipeline resource (24) to prevent disruptions to the pipeline if the branch resolves as taken during the cycle. However if the prediction is strongly not taken, the pipeline resource (24) is disabled to save power, which outweighs the infrequent resolution to taken. In one embodiment, the data processor (20) disables a branch target instruction cache (24) if history bits corresponding to the branch instruction stored in a branch history table (26) indicate strongly that the branch will not be taken.