Abstract: Multiple processors are connected to form a multiprocessor system having inter-processor communicating capability. Each processor maintains a configuration option register indicating the resources necessary to operate the multiprocessor system. In the event of a power-fail signal, indicating that possible power loss is imminent, a processor will proceed through a shut-down procedure to save the present operating state so that when power is re-applied the processor can continue from the operating state it left when power was lost. Those processors not receiving a power-fail signal will attempt to reconfigure the multiprocessor system, waiting a reasonable amount of time for the processor receiving the power-fail signal to continue operations. If the processor has not recovered from the power-fail signal after a reasonable amount of time, the other processors check the configuration option register to determine whether that processor is necessary for operation of the multiprocessor system.

Abstract: A bus controller, operable to grant access to a bus structure for communication between a number of individual processor modules interconnected by the bus to form a multiprocessor system, is also operable to determine the number of processors connected to the bus. The bus controller, in round-robin fashion, sequentially grants each processor access to the bus by commanding the processor to send data. The processor responds either by sending data in synchronism with a data clock supplied by the bus controller or, if no data is to be sent, responds with a no acknowledgment (NAK) signal. Initially, and periodically, the bus controller checks to determine the number of processors by, beginning with the highest identifying numbered processor, sending to that processor a send command, and looking for a response either in the form of data being sent or a NAK signal.

Abstract: A bus protocol system for interprocessor communications in valves polling the processors of a multiprocessor unit in an open loop fashion to determine which processors are ready to send. Upon completion of a simultaneous poll of all processors the system identifies which processor are ready to send by utilizing a send mask generated by the ready processors. The ready processors are sequentially selected as send processors and granted access to the bus for a complete data transfer cycle unless the selected processor indicates it is not ready to send. The system also includes a timing signal system that provides for a high data transfer rate. A send clock signal strobes words onto the bus from a send processor and a receive clock signal loads words from the bus to a receive processor. The send processor generates the receive clock signal by delaying the send clock signal by a fixed delay, DR.

Abstract: An electrical keying system for a set of incompatible module pairs to prevent powerup of an electrically incompatible module pair in a set.