Patents by Inventor A-Sheng Liu

A-Sheng Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955554
    Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. The plurality of the second type of epitaxial layers is oxidized in the source/drain region. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed in the opening.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huan-Sheng Wei, Hung-Li Chiang, Chia-Wen Liu, Yi-Ming Sheu, Zhiqiang Wu, Chung-Cheng Wu, Ying-Keung Leung
  • Patent number: 11956453
    Abstract: A method and apparatus for neural network based cross component prediction with scaling factors during encoding or decoding of an image frame or a video sequence, which may include training a deep neural network (DNN) cross component prediction (CCP) model with at least one or more scaling factors, wherein the at least one or more scaling factors are learned by optimizing a rate-distortion loss based on an input video sequence comprising a luma component, and reconstructing a chroma component based on the luma component using the trained DNN CCP model with the at least one or more scaling factors for chroma prediction. The trained DNN CCP may be updated for chroma prediction of the input video sequence using the one or more scaling factors, and performing chroma prediction of the input video sequence using the updated DNN CCP model with the one or more scaling factors.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: April 9, 2024
    Assignee: TENCENT AMERICA LLC
    Inventors: Sheng Lin, Wei Jiang, Wei Wang, Ding Ding, Shan Liu, Xiaozhong Xu
  • Patent number: 11952999
    Abstract: A plunger pump base and a plunger pump device. The plunger pump base includes a support assembly and an extension assembly. The support assembly includes a top plate, a bottom plate and a support frame, the top plate and the bottom plate are oppositely arranged at an interval, and the support frame is respectively fixed with the top plate and the bottom plate. The extension assembly includes an extension block, a first telescopic mechanism and a second telescopic mechanism. One end of the first telescopic mechanism is rotatably connected to the extension block, the other end of the first telescopic mechanism is rotatably connected to the top plate. One end of the second telescopic mechanism is rotatably connected to the extension block, and the other end of the second telescopic mechanism is rotatably connected to the bottom plate.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: April 9, 2024
    Assignee: Yantai Jereh Petroleum Equipment & Technologies Co., Ltd.
    Inventors: Peng Zhang, Rikui Zhang, Xiaolei Ji, Chunqiang Lan, Sheng Chang, Liang Lv, Xincheng Li, Lintao Song, Weiqiang Liu
  • Patent number: 11955865
    Abstract: A three-axis voice coil motor including a base, a spherical bearing, a magnetic component, an X-coil group, a Y-coil group, and at least one Z-coil group is provided. The base has a supporting pole. The spherical bearing is rotatably sleeved around the supporting pole. The magnetic component is securely sleeved around the spherical bearing and the magnetic component rotates along with the spherical bearing. The X-coil group is disposed around the magnetic component along an X-axial direction passing through the spherical bearing, and the X-coil group has first gaps. The Y-coil group is disposed around the magnetic component along a Y-axial direction passing through the spherical bearing, and the Y-coil group has second gaps. The Z-coil group is disposed around the magnetic component along a Z-axial direction passing through the spherical bearing.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: April 9, 2024
    Assignee: National Cheng-Kung University
    Inventors: Chien-Sheng Liu, Yi-Hsuan Lin, Chiu-Nung Yeh
  • Patent number: 11955201
    Abstract: A memory device includes a plurality of arrays coupled in parallel with each other. A first array of the plurality of arrays includes a first switch and a plurality of first memory cells that are arranged in a first column, a second switch and a plurality of second memory cells that are arranged in a second column, and at least one data line coupled to the plurality of first memory cells and the plurality of second memory cells. The second switch is configured to output a data signal from the at least one data line to a sense amplifier.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Sheng Chang, Chia-En Huang, Yi-Ching Liu, Yih Wang
  • Patent number: 11955976
    Abstract: A quadrant alternate switching phase interpolator includes first and second multiplexer circuits, a phase interpolator circuitry, and a controller circuitry. The first multiplexer circuit outputs one of first and second clock signals to be a first signal in response to first and third bits in a quadrant control code. The second multiplexer circuit outputs one of third and fourth clock signals to be a second signal in response to second and fourth bits in the quadrant control code, and the first, the third, the second, and fourth clock signals are sequentially different in phase by 90 degrees. The phase interpolator circuitry generates an output clock signal in response to the first and the second signals and phase control bits. The controller circuitry performs a bit-shift operation on the phase control bits to adjust a phase of the output clock signal.
    Type: Grant
    Filed: October 26, 2022
    Date of Patent: April 9, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yao-Chia Liu, Yuan-Sheng Lee
  • Publication number: 20240112912
    Abstract: A method of manufacturing a semiconductor device includes the following steps. A photoresist layer is formed over a material layer on a substrate. The photoresist layer has a composition including a solvent and a first photo-active compound dissolved in the solvent. The first photo-active compound is represented by the following formula (Al) or formula (A2): Zr12O8(OH)14(RCO2)18??Formula (A1); or Hf6O4(OH)6(RCO2)10??Formula (A2). R in the formula (A1) and R in the formula (A2) each include one of the following formulae (1) to (6): The photoresist layer is patterned. The material layer is etched using the photoresist layer as an etch mask.
    Type: Application
    Filed: July 28, 2023
    Publication date: April 4, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITY
    Inventors: Jui-Hsiung LIU, Yu-Fang TSENG, Pin-Chia LIAO, Burn Jeng LIN, Tsai-Sheng GAU, Po-Hsiung CHEN, Po-Wen CHIU
  • Publication number: 20240113032
    Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.
    Type: Application
    Filed: April 25, 2023
    Publication date: April 4, 2024
    Inventors: Kai-Fung CHANG, Chin-Wei LIANG, Sheng-Feng WENG, Ming-Yu YEN, Cheyu LIU, Hung-Chih CHEN, Yi-Yang LEI, Ching-Hua HSIEH
  • Publication number: 20240111210
    Abstract: A method of manufacturing a semiconductor device includes the following steps. A photoresist layer is formed over a material layer on a substrate. The photoresist layer has a composition including a solvent and a first photo-active compound dissolved in the solvent. The first photo-active compound is represented by the following formula (A1) or formula (A2): Zr12O8(OH)14(RCO2)18 ??Formula (A1); or Hf6O4(OH)6(RCO2)10 ??Formula (A2). R in the formula (A1) and R in the formula (A2) each include one of the following formulae (1) to (6): The photoresist layer is patterned. The material layer is etched using the photoresist layer as an etch mask.
    Type: Application
    Filed: May 9, 2023
    Publication date: April 4, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITY
    Inventors: Jui-Hsiung LIU, Pin-Chia LIAO, Ting-An LIN, Ting-An SHIH, Yu-Fang TSENG, Burn Jeng LIN, Tsai-Sheng GAU, Po-Hsiung CHEN, Po-Wen CHIU
  • Publication number: 20240112842
    Abstract: An inductor and a method of forming the same are provided. The inductor includes a patterned wire structure. The patterned wire structure includes a conductive core, a dielectric film and a magnetic shell. The conductive core includes a pair of end surfaces and an outer surface between the pair of end surfaces. The dielectric film covers the outer surface. The magnetic shell covers the dielectric film. The dielectric film is between the conductive core and the magnetic shell.
    Type: Application
    Filed: January 10, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Sheng Lu, Chien-Hung Liu, Nuo Xu
  • Publication number: 20240113135
    Abstract: Disclosed are a light-emitting module and a display device. The light-emitting module includes a substrate, a first driving circuit layer and at least one first light-emitting unit group. At least one first groove is provided on a surface of the substrate. The first driving circuit layer is located on the substrate and includes at least one first signal line located in the first groove. The first light-emitting unit group is located on a side, where the first driving circuit layer is provided, of the substrate, and includes at least one first lamp bead, and the first lamp bead is connected in series on the first signal line. In the light-emitting module, the first signal line is arranged in the first groove of the substrate, which is equivalent to being embedded in the substrate.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Applicant: SHINE OPTOELECTRONICS (KUNSHAN) CO., LTD.
    Inventors: Sheng ZHANG, Lixiang LIU, Shicheng ZHANG, Yi HUANG, Xiujun WANG
  • Publication number: 20240113217
    Abstract: An integrated circuit includes first and second trenches in a semiconductor substrate and a semiconductor mesa between the first and second trenches. A source region having a first conductivity type and a body region having an opposite second conductivity type are located within the semiconductor mesa. A trench shield is located within the first trench, and a gate electrode is over the trench shield between first and second sidewalls of the first trench. A gate dielectric is on a sidewall of the first trench between the gate electrode and the body region, and a pre-metal dielectric (PMD) layer is over the gate electrode. A gate contact through the PMD layer touches the gate electrode between the first and second sidewalls, and a trench shield contact through the PMD layer touches the trench shield between the first and second sidewalls.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Hong Yang, Thomas Grebs, Yunlong Liu, Sunglyong Kim, Lindong Li, Peng Li, Seetharaman Sridhar, Yeguang Zhang, Sheng pin Yang
  • Patent number: 11949892
    Abstract: A method and apparatus for neural network based cross component prediction with low-bit precision during encoding or decoding of an image frame or a video sequence, which may include reconstructing a chroma component based on a received luma component using a pre-trained deep neural network (DNN) cross component prediction (CCP) model for chroma prediction, and updating a set of parameters of the pre-trained DNN CCP model with low-bit precision. The method may also include generating an updated DNN CCP model for chroma prediction with low-bit precision based on at least one video sequence, and using the updated DNN CCP model for cross component prediction of the at least one video sequence at reduced processing time.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: April 2, 2024
    Assignee: TENCENT AMERICA LLC
    Inventors: Sheng Lin, Wei Jiang, Wei Wang, Shan Liu, Xiaozhong Xu
  • Patent number: 11945766
    Abstract: The present invention relates to the technical field of acetonitrile refining, and in particular, to an improved acetonitrile purification process for an ultrahigh performance liquid chromatography-mass spectrometer. The present invention provides an acetonitrile purification process. A high-purity finished product may be obtained by performing operations of oxidation, rectification adsorption, drying, reflux rectification and filtration on industrial acetonitrile and controlling related parameters such as temperature, flow and the like, continuous production is ensured, a light transmittance of the finished product in ultraviolet rays of 200 to 260 nm is greater than or equal to 95%, water and impurities in the industrial acetonitrile are removed, and the requirements of the ultrahigh performance liquid chromatography-mass spectrometer are met; moreover, by controlling process parameters and equipment.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: April 2, 2024
    Inventors: Sheng Wen, ZhengChong Zhao, ChunLi Gong, Fan Cheng, Hai Liu, FuQiang Hu
  • Publication number: 20240104746
    Abstract: The present invention discloses a vessel tracking and monitoring system and operating method thereof. Specifically, the vessel tracking and monitoring system comprises at least one camera, a processing module and a storage module. On the other hand, the processing module may keep the water object which is detected and recognized by the at least one camera in the center area of a monitoring screen. Therefore, the present invention may track and recognize the type of the at least one water object, assisting areas such as ports in managing and tracking water object arrivals and departures under various environmental conditions.
    Type: Application
    Filed: December 15, 2022
    Publication date: March 28, 2024
    Inventors: CHIA-YU WU, YAN-SHENG SONG, YU-TING PENG, CHIEN-HUNG LIU
  • Publication number: 20240104932
    Abstract: Systems, methods, and non-transitory computer-readable media can access a plurality of parameter-based encodings providing a structured representation of an environment captured by one or more sensors associated with a plurality of vehicles traveling through the environment. A given parameter-based encoding of the environment identifies one or more agents that were detected by a vehicle within the environment and respective location information for the one or more agents within the environment. The plurality of parameter-based encodings can be clustered into one or more clusters of parameter-based encodings. At least one scenario associated with the environment can be determined based at least in part on the one or more clusters of parameter-based encodings.
    Type: Application
    Filed: October 6, 2023
    Publication date: March 28, 2024
    Applicant: Lyft, Inc.
    Inventors: Ivan Kirigan, David Tse-Zhou Lu, Sheng Yang, Ranjith Unnikrishnan, Emilie Jeanne Anne Danna, Weiyi Hou, Daxiao Liu, Suneet Rajendra Shah, Ying Liu
  • Publication number: 20240103896
    Abstract: A computer-implemented method, system and computer program product for scaling a resource of a Database as a Service (DBaaS) cluster in a cloud platform. User service requests from a service cluster to be processed by the DBaaS cluster are received. A first set of tracing data is generated by a service mesh, which facilitates service-to-service communication between the service cluster and the DBaaS cluster, from the user service requests. A second set of tracing data is generated by the DBaaS cluster from handling the user service requests. A dependency tree is then generated to discover application relationships to identify potential bottlenecks in nodes of the DBaaS cluster based on these sets of tracing data. The pod(s) of a DBaaS node are then scaled based on the dependency tree, which is used in part, to predict the utilization of the resources of the DBaaS node identified as being a potential bottleneck.
    Type: Application
    Filed: September 24, 2022
    Publication date: March 28, 2024
    Inventors: Peng Hui Jiang, Yue Wang, Jun Su, Su Liu, Sheng Yan Sun
  • Publication number: 20240105795
    Abstract: A method for fabricating semiconductor devices is disclosed. The method includes forming a gate trench over a semiconductor channel, the gate trench being surrounded by gate spacers. The method includes sequentially depositing a work function metal, a glue metal, and an electrode metal in the gate trench. The method includes etching respective portions of the electrode metal and the glue metal to form a gate electrode above a metal gate structure. The metal gate structure includes a remaining portion of the work function metal and the gate electrode includes a remaining portion of the electrode metal. The gate electrode has an upper surface extending away from a top surface of the metal gate structure.
    Type: Application
    Filed: February 16, 2023
    Publication date: March 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jun-Ye Liu, Jih-Sheng Yang, Yu-Hsien Lin, Ryan Chia-Jen Chen
  • Patent number: 11942563
    Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.
    Type: Grant
    Filed: June 1, 2023
    Date of Patent: March 26, 2024
    Assignee: XINTEC INC.
    Inventors: Chia-Sheng Lin, Hui-Hsien Wu, Jian-Hong Chen, Tsang-Yu Liu, Kuei-Wei Chen
  • Patent number: 11943609
    Abstract: A Bluetooth communication system includes: a Bluetooth host device; and a Bluetooth device set which including a first member device and a second member device. The first member device generates a first resolvable set identifier corresponding to the first member device, and generates and transmits target Bluetooth packets containing the first resolvable set identifier to the Bluetooth host device. The second member device generates a resolvable set identifier corresponding to the second member device according to a device set identification information. The Bluetooth host device identifies the first member device as a first privileged device according to the position of the first resolvable set identifier, and transmits a first privileged pairing notice to the first member device and generates a first cypher key. The first member device further generates a second cypher key corresponding to the first cypher key after receiving the first privileged pairing notice.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: March 26, 2024
    Assignee: Realtek Semiconductor Corp.
    Inventors: Yu Hsuan Liu, Yung Chieh Lin, Po Sheng Chiu