Abstract: In some embodiments, the present disclosure relates an integrated chip including a substrate. A conductive interconnect feature is arranged over the substrate. The conductive interconnect feature has a base feature portion with a base feature width and an upper feature portion with an upper feature width. The upper feature width is narrower than the base feature width such that the conductive interconnect feature has tapered outer feature sidewalls. An interconnect via is arranged over the conductive interconnect feature. The interconnect via has a base via portion with a base via width and an upper via portion with an upper via width. The upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls.

Abstract: The present disclosure provides a method for fabricating an image sensor. The method includes the following operations. A cavity is formed at a first surface of a substrate. A germanium layer is formed in the cavity. A first heavily doped region is formed in the germanium layer by an implantation operation. A second heavily doped region is formed at a position proximal to a top surface of the germanium layer, wherein the second heavily doped region is laterally surrounded by the first heavily doped region from a top view perspective. An interconnect structure is formed over the germanium layer.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material and a passivation layer is disposed on the second semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material. A silicide is arranged within the passivation layer and along tops of the first doped region and the second doped region.

Abstract: A semiconductor device includes a package structure, a first heat spreader, and a second heat spreader. The first heat spreader is aside the package structure. The second heat spreader is in physical contact with the first heat spreader. The second heat spreader covers a top surface and sidewalls of the package structure. A material of the first heat spreader is different from a material of the second heat spreader.

Abstract: A gamma tap circuit includes: (i) a first gamma division circuit configured to generate a first gamma tap voltage by performing voltage division of an upper gamma tap voltage and a lower gamma tap voltage, in-sync with a first clock signal CK1 and a first complementary clock signal CK1b, which is 180° out-of-phase relative to CK1, (ii) a second gamma division circuit configured to generate a second gamma tap voltage by performing voltage division of the upper gamma tap voltage and the first gamma tap voltage, in-sync with a second clock signal CK2 and a second complementary clock signal CK2b, which is 180° out-of-phase relative to CK2, and (iii) a third gamma division circuit configured to generate a third gamma tap voltage by performing voltage division of the first gamma tap voltage and the lower gamma tap voltage, in response to CK2 and CK2b, which have a lower frequency relative to CK1 and CK1b.

Abstract: Some embodiments relate to a semiconductor structure. The semiconductor structure includes a first substrate including a first plurality of conductive pads that are laterally spaced apart from one another on the first substrate. A first plurality of conductive bumps are disposed on the first plurality of conductive pads, respectively. A multi-tiered solder-resist structure is disposed on the first substrate and arranged between the first plurality of conductive pads. The multi-tiered solder-resist structure has different widths at a different heights over the first substrate and contacts sidewalls of the first plurality of conductive bumps to separate the first plurality of conductive bumps from one another.

Abstract: A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.

Abstract: Embodiments of the present disclosure relate to a system, a software application, and methods of digital lithography for semiconductor packaging. The method includes comparing positions of vias and via locations, generating position data based on the comparing the positions of vias and the via locations, providing the position data of the vias to a digital lithography device, updating a redistributed metal layer (RDL) mask pattern according to the position data such that RDL locations correspond to the positions of the vias, and projecting the RDL mask pattern with the digital lithography device.

Abstract: A cell activation reactor and a cell activation method are provided. The cell activation reactor includes a body, a rotating part, an upper cover, a microporous film, and multiple baffles. The body has an accommodating space, which is suitable for accommodating multiple cells and multiple magnetic beads. The rotating part is disposed in the accommodating space and includes multiple impellers. The microporous film is disposed in the accommodating space and covers multiple holes of the accommodating space. The baffles are disposed in the body. When the rotating part is driven to rotate, the interaction between the baffles and the impellers separates the cells and the magnetic beads.

Abstract: A method for making a semiconductor structure includes: providing a substrate with a contact feature thereon; forming a dielectric layer on the substrate; etching the dielectric layer to form an interconnect opening exposing the contact feature; forming a metal layer on the dielectric layer and outside of the contact feature; and forming a graphene conductive structure on the metal layer, the graphene conductive structure filling the interconnect opening, being electrically connected to the contact feature, and having at least one graphene layer that extends in a direction substantially perpendicular to the substrate.

Abstract: Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed on and/or in a silicon substrate. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.

Abstract: The present invention discloses an integrated choke assembly comprising: a base having a main body structure, a first protruding part and a second protruding part. A first choke has a first magnetic core and a first winding, wherein the first protruding part is arranged through the first opening of the first magnetic core so that the first choke is arranged on the upper surface of the main body structure, and the first winding is wound on the first magnetic core. A second choke has a second magnetic core and a second winding, wherein the second protruding part is arranged through the second opening of the second magnetic core so that the second choke is arranged on the lower surface of the main body structure, and the second winding is wound on the second magnetic core.

Abstract: A shower head structure and a plasma processing apparatus are provided. The shower head structure includes a plate body with a first zone and a second zone on a first surface. A plurality of first through holes are in the first zone, each of the first through holes having a diameter uniform with others of the first through holes. A plurality of second through holes are in the second zone. The first zone is in connection with the second zone, and the diameter of each of the first through holes is greater than a diameter of each of the second through holes. A plasma processing apparatus includes the shower head structure is also provided.

Abstract: A semiconductor structure includes a dielectric layer over a substrate, a via conductor over the substrate and in the dielectric layer, and a first graphene layer disposed over the via conductor. In some embodiments, a top surface of the via conductor and a top surface of the dielectric layer are level. In some embodiments, the first graphene layer overlaps the via conductor from a top view. In some embodiments, the semiconductor structure further includes a second graphene layer under the via conductor and a third graphene layer between the dielectric layer and the via conductor. In some embodiments, the second graphene layer is between the substrate and the via conductor.

Abstract: A method for forming a chip package structure. The method includes bonding first connectors over a front surface of a semiconductor wafer. The method also includes dicing the semiconductor wafer from a rear surface of the semiconductor wafer to form semiconductor dies and mounting first and second semiconductor dies in the semiconductor dies over a top surface of the interposer substrate. The method further forming an encapsulating layer over the top surface of the interposer substrate to cover the first semiconductor die and the second semiconductor die. A first sidewall of the first semiconductor die faces a second sidewall of the second semiconductor die, and upper portions of the first sidewall and the second sidewall have a tapered contour, to define a top die-to-die distance and a bottom die-to-die distance that is less than the top die-to-die distance.

Abstract: A method for manufacturing a semiconductor structure includes forming a first interconnect feature in a first dielectric feature, the first interconnect feature including a first conductive element exposed from the first dielectric feature; forming a first cap feature over the first conductive element, the first cap feature including a first cap element which includes a two-dimensional material; forming a second dielectric feature with a first opening that exposes the first cap element; forming a barrier layer over the second dielectric feature while exposing the first cap element from the barrier layer; removing a portion of the first cap element exposed from the barrier layer; and forming a second conductive element in the first opening.

Abstract: A semiconductor device includes a substrate, a package structure, a first heat spreader, and a second heat spreader. The package structure is disposed on the substrate. The first heat spreader is disposed on the substrate. The first heat spreader surrounds the package structure. The second heat spreader is disposed on the package structure. The second heat spreader is connected to the first heat spreader. A material of the first heat spreader is different from a material of the second heat spreader.

Abstract: The present disclosure provides antibodies that bind to OX40 and antigen binding fragments thereof, and use of the antibodies and the antigen binding fragments in the treatment of diseases for example cancers. The antibodies or the antigen binding fragments include a heavy chain variable region including one or more CDRs having an amino acid sequence selected from amino acid sequences as set forth in SEQ ID NOs: 1-12.

Abstract: A closed-loop power control (CLPC) system is disclosed that includes a first signal path for a first polarization and a second signal path for a second polarization. The first signal path includes a first power amplifier, a first output power detector configured to detect a first output power level of the first power amplifier, and a first processor configured to determine a first analog gain for a first controller and a first gain for a first digital-to-analog converter based on a first accumulated error between the first output power level and a target Effective Isotropically Radiated Power. A second processor is configured to set a first variable gain of a first variable gain amplifier coupled to an input of the first power amplifier. The CLPC can be configured to control the gain of the first signal path separately or as one signal path.