Patents by Inventor A. T. Look
A. T. Look has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220062291Abstract: Disclosed are compositions and methods of treating cancers by constitutively activating protein phosphatase 2A (PP2A) without blocking signaling through the dopamine D2 receptor, that entail administering a therapeutically effective amount of an analog of perphenazine (PPZ) of formula (I) or (II), or a related PPZ analog lacking dopamine receptor D2 inhibitory activity, or a pharmaceutically acceptable salt thereof.Type: ApplicationFiled: December 19, 2019Publication date: March 3, 2022Applicant: DANA-FARBER CANCER INSTITUTE, INC.Inventors: Alfred T. Look, Ken Morita, Eric S. Fischer, Nathanael S. Gray, Shuning He
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Patent number: 9041409Abstract: An integrated circuit structure can include a plurality of solder bumps coupled in series forming a chain and a plurality of diodes, wherein each diode is coupled to one of the plurality of solder bumps. The integrated circuit structure also can include a first pad coupled to the solder bump of the plurality of solder bumps at an end of the chain. The first pad can be configured to provide a test current responsive to application of a forward bias voltage to each diode of the plurality of diodes.Type: GrantFiled: January 11, 2012Date of Patent: May 26, 2015Assignee: XILINX, INC.Inventor: Kevin T. Look
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Patent number: 7810104Abstract: A controller for an instrument includes a control program, an object that interfaces between the control program and the device, and a discovery process. The control program is used by the controller to provide software control of a device within the instrument. The object contains control information about the device so that the control information does not need to be known by the control program. The control information is needed to control the device. The discovery process, upon discovery that the device is within the instrument, obtains the control information from data storage within the instrument and instantiates the object.Type: GrantFiled: April 4, 2007Date of Patent: October 5, 2010Assignee: Agilent Technologies, Inc.Inventors: Michael T. Look, Douglas G. Yule, Jr.
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Patent number: 7504854Abstract: A method of operating a programmable logic device, including the steps of using a full VDD supply voltage to operate one or more active blocks of the programmable logic device, and using a reduced supply voltage (e.g., ½ VDD) to operate one or more inactive blocks of the programmable logic device. The full VDD supply voltage and reduced supply voltage can be provided to the blocks of the programmable logic device through high-voltage n-channel transistors. A boosted voltage, greater than VDD, is applied to the gate of an n-channel transistor to provide the full VDD supply voltage to an active block. A standby voltage, less than VDD, is applied to the gate of an n-channel transistor to provide the reduced supply voltage to an inactive block. The inactive blocks can be determined during run time and/or design time of the programmable logic device.Type: GrantFiled: February 20, 2004Date of Patent: March 17, 2009Assignee: Xilinx, Inc.Inventors: Kevin T. Look, Michael J. Hart, Tim Tuan, Kameswara K. Rao, Robert O. Conn
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Patent number: 7452765Abstract: SEU-hardening series resistances loads are formed within the gate structures of cross-coupled inverters of a latch. For some embodiments, the gate contact for the input of each cross-coupled inverter has a sufficiently high resistance to provide the SEU-hardening series resistance. For other embodiments, a conductive trace layer coupled to the input of each cross-coupled inverter includes a high-resistivity portion that provides the SEU-hardening series resistance.Type: GrantFiled: September 30, 2005Date of Patent: November 18, 2008Assignee: XILINX, Inc.Inventors: Martin L. Voogel, Austin H. Lesea, Joseph J. Fabula, Carl H. Carmichael, Shahin Toutounchi, Michael J. Hart, Steven P. Young, Kevin T. Look, Jan L. de Jong
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Publication number: 20080250428Abstract: A controller for an instrument includes a control program, an object that interfaces between the control program and the device, and a discovery process. The control program is used by the controller to provide software control of a device within the instrument. The object contains control information about the device so that the control information does not need to be known by the control program. The control information is needed to control the device. The discovery process, upon discovery that the device is within the instrument, obtains the control information from data storage within the instrument and instantiates the object.Type: ApplicationFiled: April 4, 2007Publication date: October 9, 2008Inventors: Michael T. Look, Douglas G. Yule
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Patent number: 7092273Abstract: A p-channel non-volatile memory (NVM) transistor is programmed by shifting the threshold voltage of the transistor. The threshold voltage is shifted by introducing a programming current to the gate electrode of the transistor, and simultaneously introducing a negative bias to the transistor. The threshold voltage of the p-channel NVM transistor is shifted in response to the negative bias condition and the heat generated by the programming current. The high temperature accelerates the threshold voltage shift. The threshold voltage shift is accompanied by an agglomeration of material in the gate electrode. The agglomeration of material in the gate electrode is an indication of the high temperature reached during programming. The threshold voltage shift of the p-channel NVM transistor is permanent.Type: GrantFiled: February 14, 2006Date of Patent: August 15, 2006Assignee: Xilinx Inc.Inventor: Kevin T. Look
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Patent number: 7026692Abstract: A p-channel non-volatile memory (NVM) transistor is programmed by shifting the threshold voltage of the transistor. The threshold voltage is shifted by introducing a programming current to the gate electrode of the transistor, and simultaneously introducing a negative bias to the transistor. The threshold voltage of the p-channel NVM transistor is shifted in response to the negative bias condition and the heat generated by the programming current. The high temperature accelerates the threshold voltage shift. The threshold voltage shift is accompanied by an agglomeration of material in the gate electrode. The agglomeration of material in the gate electrode is an indication of the high temperature reached during programming. The threshold voltage shift of the p-channel NVM transistor is permanent.Type: GrantFiled: November 12, 2003Date of Patent: April 11, 2006Assignee: Xilinx, Inc.Inventor: Kevin T. Look
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Patent number: 6982451Abstract: SEU-hardening series resistances loads are formed within the gate structures of cross-coupled inverters of a latch. For some embodiments, the gate contact for the input of each cross-coupled inverter has a sufficiently high resistance to provide the SEU-hardening series resistance. For other embodiments, a conductive trace layer coupled to the input of each cross-coupled inverter includes a high-resistivity portion that provides the SEU-hardening series resistance.Type: GrantFiled: March 27, 2003Date of Patent: January 3, 2006Assignee: Xilinx, Inc.Inventors: Martin L. Voogel, Austin H. Lesea, Joseph J. Fabula, Carl H. Carmichael, Shahin Toutounchi, Michael J. Hart, Steven P. Young, Kevin T. Look, Jan L. de Jong
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Patent number: 6936527Abstract: A memory cell comprises a multilayer gate heating structure formed over a channel region between source and drain regions. The multilayer gate heating structure comprises polysilicon and metal silicide layers stacked over a similarly shaped gate oxide. When a programming voltage is applied across the metal silicide layer, there is intense localized heating. The heating causes segregation of the channel dopant atoms towards the source and drain regions, lowering the threshold voltage of the device. The heating causes carrier activation in the polysilicon layer and dopant penetration through the oxide layer into the channel region, thereby increasing the threshold voltage of the device.Type: GrantFiled: October 24, 2003Date of Patent: August 30, 2005Assignee: Xilinx, Inc.Inventor: Kevin T. Look
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Patent number: 6930920Abstract: A memory cell comprises a multilayer gate heating structure formed over a channel region between source and drain regions. The multilayer gate heating structure comprises polysilicon and metal silicide layers stacked over a similarly shaped gate oxide. When a programming voltage is applied across the metal silicide layer, there is intense localized heating. The heating causes segregation of the channel dopant atoms towards the source and drain regions, lowering the threshold voltage of the device. The heating causes carrier activation in the polysilicon layer and dopant penetration through the oxide layer into the channel region, thereby increasing the threshold voltage of the device.Type: GrantFiled: October 24, 2003Date of Patent: August 16, 2005Assignee: Xilinx, Inc.Inventor: Kevin T. Look
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Patent number: 6882571Abstract: A memory cell comprises a multilayer gate heating structure formed over a channel region between source and drain regions. The multilayer gate heating structure comprises polysilicon and metal silicide layers stacked over a similarly shaped gate oxide. When a programming voltage is applied across the metal silicide layer, there is intense localized heating. The heating causes segregation of the channel dopant atoms towards the source and drain regions, lowering the threshold voltage of the device. The heating causes carrier activation in the polysilicon layer and dopant penetration through the oxide layer into the channel region, thereby increasing the threshold voltage of the device.Type: GrantFiled: October 24, 2003Date of Patent: April 19, 2005Assignee: Xilinx, Inc.Inventor: Kevin T. Look
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Patent number: 6878561Abstract: Described are mask-alignment detection structures that measure both the direction and extent of misalignment between layers of an integrated circuit using resistive elements for which resistance varies with misalignment in one dimension. Measurements in accordance with the invention are relatively insensitive to process variations, and the structures using to take these measurements can be formed along with other features on an integrated circuit using standard processes. One embodiment of the invention may be used to measure misalignment between two conductive layers. Other embodiments measure misalignment between diffusion regions and conductors and between diffusion regions and windows through which other diffusion regions are to be formed. A circuit in accordance with one embodiment includes row and column decoders for independently selecting mask-alignment detection structures to reduce the number of test terminals required to implement the detection structures.Type: GrantFiled: October 7, 2003Date of Patent: April 12, 2005Assignee: Xilinx, Inc.Inventors: Kevin T. Look, Shih-Cheng Hsueh
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Publication number: 20040072398Abstract: Described are mask-alignment detection structures that measure both the direction and extent of misalignment between layers of an integrated circuit using resistive elements for which resistance varies with misalignment in one dimension. Measurements in accordance with the invention are relatively insensitive to process variations, and the structures using to take these measurements can be formed along with other features on an integrated circuit using standard processes. One embodiment of the invention may be used to measure misalignment between two conductive layers. Other embodiments measure misalignment between diffusion regions and conductors and between diffusion regions and windows through which other diffusion regions are to be formed. A circuit in accordance with one embodiment includes row and column decoders for independently selecting mask-alignment detection structures to reduce the number of test terminals required to implement the detection structures.Type: ApplicationFiled: October 7, 2003Publication date: April 15, 2004Applicant: Xilinx, Inc.Inventors: Kevin T. Look, Shih-Cheng Hsueh
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Patent number: 6716653Abstract: An electrical alignment test structure enables monitoring and measuring misalignment between layers (or associated masks) of an IC. The alignment test structure comprises a target region and an alignment feature in different layers. The target region and the alignment feature may be formed in diffusion and polysilicon layers, respectively or in well and diffusion layers, respectively. In both embodiments, the alignment feature controls the size of a conductive channel in the target region. Misalignment can be checked by comparing channel resistance with a baseline (no misalignment) resistance. In another embodiment, the target region and alignment feature are formed in the diffusion and polysilicon layers, respectively, wherein the alignment feature controls the relative widths of the source and drain regions. Misalignment can be checked by comparing current flow with a baseline current.Type: GrantFiled: October 24, 2002Date of Patent: April 6, 2004Assignee: Xilinx, Inc.Inventors: Kevin T. Look, Shih-Cheng Hsueh
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Patent number: 6684520Abstract: Described are mask-alignment detection structures that measure both the direction and extent of misalignment between layers of an integrated circuit using resistive elements for which resistance varies with misalignment in one dimension. Measurements in accordance with the invention are relatively insensitive to process variations, and the structures using to take these measurements can be formed along with other features on an integrated circuit using standard processes. One embodiment of the invention may be used to measure misalignment between two conductive layers. Other embodiments measure misalignment between diffusion regions and conductors and between diffusion regions and windows through which other diffusion regions are to be formed. A circuit in accordance with one embodiment includes row and column decoders for independently selecting mask-alignment detection structures to reduce the number of test terminals required to implement the detection structures.Type: GrantFiled: February 25, 2000Date of Patent: February 3, 2004Assignee: Xilinx, Inc.Inventors: Kevin T. Look, Shih-Cheng Hsueh
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Patent number: 6671205Abstract: A memory cell comprises a multilayer gate heating structure formed over a channel region between source and drain regions. The multilayer gate heating structure comprises polysilicon and metal silicide layers stacked over a similarly shaped gate oxide. When a programming voltage is applied across the metal silicide layer, there is intense localized heating. The heating causes segregation of the channel dopant atoms towards the source and drain regions, lowering the threshold voltage of the device. The heating causes carrier activation in the polysilicon layer and dopant penetration through the oxide layer into the channel region, thereby increasing the threshold voltage of the device.Type: GrantFiled: October 29, 2002Date of Patent: December 30, 2003Assignee: Xilinx, Inc.Inventor: Kevin T. Look
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Patent number: 6569576Abstract: A reticle and pellicle that are modified to prevent ESD damage to the masking material between portions of the lithographic mask pattern on the reticle during an integrated circuit fabrication process. The modification involves providing conducting lines on the glass side of the reticle and on the surface of the pellicle to balance any buildup of electrostatic charges on those devices, thereby reducing or eliminating the induction of opposite charges onto adjacent mask pattern features on the reticle and preventing the melting and bridging of those mask pattern features and the defects caused by such melting or bridging. The conductive metal lines may have a smaller width than the smallest resolution value of the reduction lens used in the mask pattern transfer process, and may also be located outside of the focal plane of the reduction lens to avoid transfer of the images of the conductive lines onto the target semiconductor substrate during the mask pattern transfer process.Type: GrantFiled: September 27, 2000Date of Patent: May 27, 2003Assignee: Xilinx, Inc.Inventors: Shih-Cheng Hsueh, Kevin T. Look, Jonathan Jung-Ching Ho
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Patent number: 6563320Abstract: An electrical alignment test structure enables monitoring and measuring misalignment between layers (or associated masks) of an IC. The alignment test structure comprises a target region and an alignment feature in different layers. The target region and the alignment feature may be formed in diffusion and polysilicon layers, respectively or in well and diffusion layers, respectively. In both embodiments, the alignment feature controls the size of a conductive channel in the target region. Misalignment can be checked by comparing channel resistance with a baseline (no misalignment) resistance. In another embodiment, the target region and alignment feature are formed in the diffusion and polysilicon layers, respectively, wherein the alignment feature controls the relative widths of the source and drain regions. Misalignment can be checked by comparing current flow with a baseline current.Type: GrantFiled: December 15, 2000Date of Patent: May 13, 2003Assignee: Xilinx, Inc.Inventors: Kevin T. Look, Shih-Cheng Hsueh
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Patent number: 6549458Abstract: Memory cell structures and related circuitry for use in non-volatile memory devices can be fabricated utilizing standard CMOS processes, for example, 0.18 micron or 0.15 micron processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials, for example, between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming.Type: GrantFiled: October 25, 2001Date of Patent: April 15, 2003Assignee: Xilinx, Inc.Inventors: Kameswara K. Rao, Martin L. Voogel, James Karp, Shahin Toutounchi, Michael J. Hart, Daniel Gitlin, Kevin T. Look, Jongheon Jeong, Radko G. Bankras