Patents by Inventor A. Van Norstrand
A. Van Norstrand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11768684Abstract: Disclosed is a method for rebalancing blocks of a register file. The method comprises allocating a first set of entries in a first register file to a first hardware thread of a processor core. The method further comprises allocating a second set of entries in a second register file to a second hardware thread of the processor core. The register tags in the first and second register files are compacted such that register tags associated with the first hardware thread are compacted into the first set of entries, and register tags associated with the second hardware thread are compacted into the second set of entries.Type: GrantFiled: August 27, 2020Date of Patent: September 26, 2023Assignee: International Business Machines CorporationInventors: Steven J. Battle, Dung Q. Nguyen, Albert J. Van Norstrand, Jr., Tu-An T. Nguyen, Cliff Kucharski
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Publication number: 20220066830Abstract: Disclosed is a method for rebalancing blocks of a register file. The method comprises allocating a first set of entries in a first register file to a first hardware thread of a processor core. The method further comprises allocating a second set of entries in a second register file to a second hardware thread of the processor core. The register tags in the first and second register files are compacted such that register tags associated with the first hardware thread are compacted into the first set of entries, and register tags associated with the second hardware thread are compacted into the second set of entries.Type: ApplicationFiled: August 27, 2020Publication date: March 3, 2022Inventors: Steven J. Battle, Dung Q. Nguyen, Albert J. Van Norstrand, JR., Tu-An T. Nguyen, Cliff Kucharski
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Patent number: 11144319Abstract: In an approach to dynamic redistribution of register files, whether a redistribution of register files is necessary is determined. Responsive to determining that the redistribution of register files is necessary, one or more register file transfers that have not yet completed are flushed. One or more register file write locations are allocated for each architected register based on a register free list. Source data is read from each architected register. The source data is written to the one or more register file write locations.Type: GrantFiled: July 28, 2020Date of Patent: October 12, 2021Assignee: International Business Machines CorporationInventors: Steven J. Battle, Susan E. Eisen, Dung Q. Nguyen, Salma Ayub, Albert J. Van Norstrand, Jr., Kent Li, Kurt A. Feiste, Christian Gerhard Zoellin
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Patent number: 11068274Abstract: A simultaneous multithreading processor is configured to select a first thread of the plurality of threads according to a predefined scheme, and access an instruction completion table to determine whether the first thread is eligible to have a first instruction prioritized. Responsive to determining that the first thread is eligible to have the first instruction prioritized, the simultaneous multithreading processor is further configured to execute the first instruction of the first thread using a dedicated prioritization resource.Type: GrantFiled: December 15, 2017Date of Patent: July 20, 2021Assignee: International Business Machines CorporationInventors: Kenneth L. Ward, Susan E. Eisen, Dung Q. Nguyen, Albert J. Van Norstrand, Jr., Glenn O. Kincaid, Christopher M. Mueller
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Patent number: 10983800Abstract: A processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues provides flexible and efficient use of internal resources. The configuration of the execution slices is selectable so that capabilities of the processor core can be adjusted according to execution requirements for the instruction streams. A plurality of load-store slices coupled to the execution slices provides access to a plurality of cache slices that partition the lowest level of cache memory among the load-store slices.Type: GrantFiled: June 6, 2018Date of Patent: April 20, 2021Assignee: International Business Machines CorporationInventors: Lee Evan Eisen, Hung Qui Le, Jentje Leenstra, Jose Eduardo Moreira, Bruce Joseph Ronchetti, Brian William Thompto, Albert James Van Norstrand, Jr.
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Patent number: 10909034Abstract: Techniques are disclosed for performing issue queue snooping for an asynchronous flush and restore of a history buffer (HB) in a processing unit. One technique includes identifying an entry of the HB to restore to a register file in the processing unit. A restore ITAG of the HB entry is sent to the register file via a first restore bus, and restore data of the HB entry and the restore ITAG is sent to the register file via a second restore bus. After the restore ITAG and restore data are sent, an instruction is dispatched before the register file obtains the restore data. After it is determined that the restore data is still available via the second restore bus, a snooping operation is performed to obtain the restore data from the second restore bus for the dispatched instruction.Type: GrantFiled: December 18, 2017Date of Patent: February 2, 2021Assignee: International Business Machines CorporationInventors: David R. Terry, Dung Q. Nguyen, Brian W. Thompto, Joshua W. Bowman, Steven J. Battle, Sundeep Chadha, Brian D. Barrick, Albert J. Van Norstrand, Jr.
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Patent number: 10884742Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.Type: GrantFiled: August 27, 2019Date of Patent: January 5, 2021Assignee: International Business Machines CorporationInventors: Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen, Brian W. Thompto, Albert J. Van Norstrand, Jr.
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Patent number: 10831481Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.Type: GrantFiled: June 6, 2019Date of Patent: November 10, 2020Assignee: International Business Machines CorporationInventors: Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen, Brian W. Thompto, Albert J. Van Norstrand
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Patent number: 10831492Abstract: Systems, methods, and computer program products are disclosed that control issuing branch instructions in a simultaneous multi-threading (SMT) system. An embodiment system includes an SMT processor circuit that receives, from one of a plurality of threads, a branch instruction having a favor bit. The SMT processor circuit schedules the branch instruction to issue, relative to branch instructions received from other threads in the plurality of threads, based on the favor bit. When the favor bit has a first value, the branch instruction is scheduled to have a higher priority to issue before the branch instructions received from other threads in the plurality of threads. When the favor bit has a second value, the branch instruction is scheduled to issue based an age of the branch instruction relative to respective ages of the branch instructions received from other threads in the plurality of threads.Type: GrantFiled: July 5, 2018Date of Patent: November 10, 2020Assignee: International Business Machines CorporationInventors: Salma Ayub, Glenn O. Kincaid, Christopher M. Mueller, Dung Q. Nguyen, Eula Faye Abalos Tolentino, Albert J. Van Norstrand, Jr., Kenneth L. Ward
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Patent number: 10552162Abstract: Variable latency flush filtering including receiving a first flush instruction tag (ITAG) and a second flush ITAG, wherein the first flush ITAG and the second flush ITAG are instructions to invalidate internal operation results after an internal operation identified by the first flush ITAG and the second flush ITAG; determining that the second flush ITAG is before the first flush ITAG by comparing the first flush ITAG and the second flush ITAG; determining that the first flush ITAG requires adjustment; and delaying the flush to a subsequent cycle in response to determining that the second flush ITAG is before the first flush ITAG and determining that the first flush ITAG requires adjustment.Type: GrantFiled: January 22, 2018Date of Patent: February 4, 2020Assignee: International Business Machines CorporationInventors: Glenn O. Kincaid, David S. Levitan, Albert J. Van Norstrand, Jr.
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Patent number: 10552165Abstract: Within a processor, speculative finishes of load instructions only are tracked in a speculative finish table by maintaining an oldest load instruction of a thread in the speculative finish table after data is loaded for the oldest load instruction, wherein a particular queue index tag assigned to the oldest load instruction by an execution unit points to a particular entry in the speculative finish table, wherein the oldest load instruction is waiting to be finished dependent upon an error check code result. Responsive to a flow unit receiving the particular queue index tag with an indicator that the error check code result for data retrieved for the oldest load instruction is good, finishing the oldest load instruction in the particular entry pointed to by the queue index tag and writing an instruction tag stored in the entry for the oldest load instruction out of the speculative finish table for completion.Type: GrantFiled: October 19, 2015Date of Patent: February 4, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Susan E. Eisen, David A. Hrusecky, Christopher M. Mueller, Dung Q. Nguyen, A. James Van Norstrand, Jr., Kenneth L. Ward
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Patent number: 10545765Abstract: Embodiments include systems, methods, and computer program products for using a multi-level history buffer (HB) for a speculative transaction. One method includes after dispatching a first instruction indicating start of the speculative transaction, marking one or more register file (RF) entries as pre-transaction memory (PTM), and after dispatching a second instruction targeting one of the marked RF entries, moving data from the marked RF entry to a first level HB entry and marking the first level HB entry as PTM. The method also includes upon detecting a write back to the first level HB entry, moving data from the first level HB entry to a second level HB entry and marking the second level HB entry as PTM. The method further includes upon determining that the second level HB entry has been completed, moving data from the second level HB entry to a third level HB entry.Type: GrantFiled: May 17, 2017Date of Patent: January 28, 2020Assignee: International Business Machines CorporationInventors: Brian D. Barrick, Steven J. Battle, Joshua W. Bowman, Hung Q. Le, Dung Q. Nguyen, David R. Terry, Albert J. Van Norstrand, Jr.
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Publication number: 20200019405Abstract: A split level history buffer in a central processing unit is provided. The history buffer includes first, second, and third levels, each having different characteristics. Operational instructions are provided to support the split history buffer. A first instruction is fetched, tagged, and stored in an entry of a register file. As a second instruction is fetched and tagged, the first instruction is evicted from the register file and stored in the first level of the history buffer. Similarly, as a result for the first instruction is generated, the first instruction and the generated result are stored in the second level of the history buffer. In response to instruction completion, instead of remaining in the second level, the first instruction, which contains pre-transactional memory checkpoint data, is moved from the second level to the third level of the history buffer, together with pre-transactional memory data, and the first instruction entry in the second level is invalidated.Type: ApplicationFiled: July 15, 2018Publication date: January 16, 2020Applicant: International Business Machines CorporationInventors: Steven J. Battle, Joshua W. Bowman, Dung Q. Nguyen, Albert J. Van Norstrand, JR., Cliff Kucharski, Hung Q. Le, Brian D. Barrick
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Publication number: 20200012496Abstract: Systems, methods, and computer program products are disclosed that control issuing branch instructions in a simultaneous multi-threading (SMT) system. An embodiment system includes an SMT processor circuit that receives, from one of a plurality of threads, a branch instruction having a favor bit. The SMT processor circuit schedules the branch instruction to issue, relative to branch instructions received from other threads in the plurality of threads, based on the favor bit. When the favor bit has a first value, the branch instruction is scheduled to have a higher priority to issue before the branch instructions received from other threads in the plurality of threads. When the favor bit has a second value, the branch instruction is scheduled to issue based an age of the branch instruction relative to respective ages of the branch instructions received from other threads in the plurality of threads.Type: ApplicationFiled: July 5, 2018Publication date: January 9, 2020Inventors: Salma Ayub, Glenn O. Kincaid, Christopher M. Mueller, Dung Q. Nguyen, Eula Faye Abalos Tolentino, Albert J. Van Norstrand, Jr., Kenneth L. Ward
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Patent number: 10528352Abstract: Blocking instruction fetching in a computer processor, includes: receiving a non-branching instruction to be executed by the computer processor; determining whether executing the non-branching instruction will cause a flush; and responsive to determining that executing the non-branching instruction will cause a flush, disabling instruction fetching for the computer processor for a time, including recoding the instruction such that the recoded instruction will be interpreted by an instruction fetch unit as an unconditional branch instruction.Type: GrantFiled: March 8, 2016Date of Patent: January 7, 2020Assignee: International Business Machines CorporationInventors: Bryan G. Hickerson, Sheldon Levenstein, David S. Levitan, Albert J. Van Norstrand, Jr.
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Publication number: 20190384602Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.Type: ApplicationFiled: August 27, 2019Publication date: December 19, 2019Inventors: SUNDEEP CHADHA, ROBERT A. CORDES, DAVID A. HRUSECKY, HUNG Q. LE, JENTJE LEENSTRA, DUNG Q. NGUYEN, BRIAN W. THOMPTO, ALBERT J. VAN NORSTRAND, JR.
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Patent number: 10496406Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.Type: GrantFiled: June 21, 2018Date of Patent: December 3, 2019Assignee: International Business Machines CorporationInventors: Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen, Brian W. Thompto, Albert J. Van Norstrand, Jr.
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Patent number: 10467008Abstract: Methods and apparatus for identifying an effective address (EA) using an interrupt instruction tag (ITAG) in a multi-slice processor including receiving, by an instruction fetch unit of the processor, the interrupt ITAG; retrieving an effective address table (EAT) row from an EAT, wherein the EAT row comprises a range of EAs and a first ITAG of a range of ITAGs; accessing a processor instruction vector comprising a plurality of elements, each element corresponding to one of a plurality of ITAGs; applying a mask to the processor instruction vector to obtain a portion of the processor instruction vector that begins with an element corresponding to the first ITAG and is defined by an element corresponding to the interrupt ITAG; calculating an EA offset; and identifying the EA for the interrupt ITAG using the EA offset and the range of EAs in the retrieved EAT row.Type: GrantFiled: May 31, 2016Date of Patent: November 5, 2019Assignee: International Business Machines CorporationInventors: David S. Levitan, Mehul Patel, Albert J. Van Norstrand, Jr., Phillip G. Williams
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Patent number: 10423423Abstract: Within a processor, speculative finishes of load instructions only are tracked in a speculative finish table by maintaining an oldest load instruction of a thread in the speculative finish table after data is loaded for the oldest load instruction, wherein a particular queue index tag assigned to the oldest load instruction by an execution unit points to a particular entry in the speculative finish table, wherein the oldest load instruction is waiting to be finished dependent upon an error check code result. Responsive to a flow unit receiving the particular queue index tag with an indicator that the error check code result for data retrieved for the oldest load instruction is good, finishing the oldest load instruction in the particular entry pointed to by the queue index tag and writing an instruction tag stored in the entry for the oldest load instruction out of the speculative finish table for completion.Type: GrantFiled: September 29, 2015Date of Patent: September 24, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Susan E. Eisen, David A. Hrusecky, Christopher M. Mueller, Dung Q. Nguyen, A. James Van Norstrand, Jr., Kenneth L. Ward
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Publication number: 20190286446Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.Type: ApplicationFiled: June 6, 2019Publication date: September 19, 2019Inventors: SUNDEEP CHADHA, ROBERT A. CORDES, DAVID A. HRUSECKY, HUNG Q. LE, JENTJE LEENSTRA, DUNG Q. NGUYEN, BRIAN W. THOMPTO, ALBERT J. VAN NORSTRAND, Jr.