Abstract: A method of forming a three-dimensional (3D) memory device includes: forming, over a substrate, a layer stack having alternating layers of a first conductive material and a first dielectric material; forming trenches extending vertically through the layer stack from an upper surface of the layer stack distal from the substrate to a lower surface of the layer stack facing the substrate; lining sidewalls and bottoms of the trenches with a memory film; forming a channel material over the memory film, the channel material including an amorphous material; filling the trenches with a second dielectric material after forming the channel material; forming memory cell isolation regions in the second dielectric material; forming source lines (SLs) and bit lines (BLs) that extend vertically in the second dielectric material on opposing sides of the memory cell isolation regions; and crystallizing first portions of the channel material after forming the SLs and BLs.

Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.

Abstract: A head-mounted device includes a first light field camera, a second light field camera, a first light field display, a second light field display and a supporting structure. Each of the first light field camera and the second light field camera includes, in order from an object side to an image side, a lens group, a collimator and an image sensor. Each of the lens groups includes a plurality of lens units. The lens units are arranged in a two-dimensional lens array, and each of the lens units includes a lens container and a plurality of lens elements. A first engaging structure is disposed between at least two adjacent lens elements of the lens elements.

Abstract: A method (and structure and computer product) to permit zero-shot voice conversion with non-parallel data includes receiving source speaker speech data as input data into a content encoder of a style transfer autoencoder system, the content encoder providing a source speaker disentanglement of the source speaker speech data by reducing speaker style information of the input source speech data while retaining content information and receiving target speaker input speech as input data into a target speaker encoder. The output of the content encoder and the target speaker encoder are combined in a decoder of the style transfer autoencoder, and the output of the decoder provides the content information of the input source speech data in a style of the target speaker speech information.

Abstract: A package structure is provided. The package structure includes a first conductive pad in an insulating layer, a first under bump metallurgy structure under the first insulating layer, and a first conductive via in the insulating layer. The first conductive via is vertically connected to the first conductive pad and the first under bump metallurgy structure. In a plan view, a first area of the first under bump metallurgy structure is confined within a second area of the first conductive pad.

Abstract: Embodiments of the present application relate to polymers used as polymeric polyvalent hub for liquid phase oligonucleotide synthesis. Methods for making an oligonucleotide by liquid phase oligonucleotide synthesis using the polyvalent hub are also provided.

Abstract: The present disclosure provides a driving circuit of a display device and the display device. The driving circuit includes an input unit, a control unit coupled to the input unit, and a light emitting unit coupled to the control unit. The control unit is configured to drive the light emitting unit to emit light. the control unit comprises a pulse width modulation (PWM) control unit and a pulse amplitude modulation (PAM) control unit, the PWM control unit and the PAM control unit are mutually independent, the PWM control unit is configured to control a light emitting time of the light emitting unit, and the PAM control unit is configured to control a magnitude of a driving current in the light emitting unit.

Abstract: A voltage regulating device and a mode switching detecting circuit are provided. The mode switching detecting circuit is configured to reset a soft start circuit of the voltage regulating device. The mode switching detecting circuit includes a mode switching signal detector, a reset signal generator, and a reset status detector. The mode switching signal detector receives a mode switching signal and generates a setting signal according to a transition edge of the mode switching signal. The reset signal generator is coupled to the mode switching signal detector and generates a reset activating signal according to the setting signal. The reset activating signal drives the soft start circuit to perform a reset operation. The reset status detector compares an output voltage of the soft start circuit and a reference voltage to generate a clear signal. The reset signal generator clears the reset activating signal according to the clear signal.

Abstract: To reduce the amount of space occupied in the inactive area of a display by gate driver circuitry, at least a portion of the gate driver circuitry may be positioned in the active area of the display. To accommodate the gate driver circuitry, emissive sub-pixels may be laterally shifted relative to corresponding thin-film transistor sub-pixels. This allows for the thin-film transistor sub-pixels to be grouped adjacent to the central area of the active area, leaving room along an edge of the active area to accommodate one or more additional display components such as gate driver circuitry or fanout portions of data lines.

Abstract: A data synchronization method, device, equipment, system and storage medium. Including: if a first data packet received by a slave device from a master device during a current Bluetooth low energy (BLE) connection interval is a new data packet, the slave device generates a hardware synchronization signal, which is a synchronization signal generated by a pure hardware circuit; if a data synchronization time of the slave device with the master device is a preset time in the current BLE connection interval, then the slave device performs data synchronization with the master device at the data synchronization time through triggering by the hardware synchronization signal.

Abstract: A method for controlling mobility of a terminal includes: after receiving configuration of a Signal Radio Bearer (SRB) 1, the terminal enters a Radio Resource Control (RRC) connected state; in response to that the terminal in the RRC connected state does not receive configuration of a Data Radio Bearer (DRB) and/or configuration of an SRB2, the terminal reports, based on measurement configuration of the network side, a measurement result to the network side, wherein the measurement result is used by the network side to determine a target cell; and the terminal receives an RRC release message from the network side, wherein the RRC release message carries reference information of the target cell.

Abstract: A modified Ni—Ti—Ta dielectric material for multi-layer ceramic capacitor (MLCC) and a low-temperature preparation method thereof are provided. By using characteristics that radii of the Cu2+ ion and (Al1/2Nb1/2)4+ ion are close to those of Ni and Ti elements, respectively, Cu2+, Al3+ and Nb5+ ions are introduced into a Ni0.5Ti0.5TaO4 matrix for partial substitution, a negative temperature coefficient of dielectric constant of ?220±30 ppm/° C. is provided while a sintering temperature is significantly reduced, and deterioration factors of loss caused by sintering aids is reduced, so that the dielectric material applied to radio frequency MLCC with low loss, low cost and good process stability is prepared.

Abstract: An intra prediction method and device and a computer-readable storage medium, the method comprising: configuring actual angle modes indicated by relative angle numbers, wherein the relative angle numbers are successively represented within a prediction direction range corresponding to a preset width and height relationship; starting from a starting angle, using a corresponding actual angle mode after sampling preset angle sample points, said starting angle being determined according to the width and height relationship of processing blocks and the prediction direction range corresponding to the preset width and height relationship, and actual angles having a one-to-one correspondence with the actual angle modes.

Abstract: The present disclosure in at least one embodiment provides a wireless communication device, comprising a lower case, an upper radome, coupled to the lower case, creating a storage space between the lower case and the upper radome, an antenna disposed in the storage space, and a plurality of internal substrates, disposed between the antenna and the lower case in the storage space, of which one of the plurality of internal substrates is connected to the antenna, wherein each internal substrate of the plurality of internal substrates is disposed along a first direction parallel to a surface of the lower case facing the plurality of internal substrates.

Abstract: An optical keyswitch includes a keycap, a support mechanism, and a switch module. The support mechanism is disposed below the keycap and configured to support the keycap moving upward and downward, the support mechanism comprising a first frame and a second frame, the first frame having a sliding end. The switch module includes a circuit board, an emitter, and a receiver, the emitter and the receiver are electrically connected to the circuit board, and the emitter emitting an optical signal to the receiver. When the keycap is pressed, the first frame is driven by the keycap to slide substantially parallel to the circuit board and block the optical signal with the sliding end, so the switch module is triggered to generate a triggering signal.

Abstract: An asymmetrical I/O structure is provided. In one embodiment, the asymmetrical I/O structure comprises a first power supply node connected to a first voltage, a second power supply node connected to a second voltage, a pull-up unit and a pull-down unit which are connected between the first power supply node and the second power supply node. The first voltage is higher than the second voltage. A node between the pull-up unit and the pull-down unit is connected to an I/O node. The pull-up unit comprises one or more pull-up transistors, and the pull-down unit comprises one or more pull-down transistors. The number of the pull-up transistors is different from the number of the pull-down transistors.

Abstract: Systems and methods for creating, monitoring, and managing a breakout conference for a conference call are disclosed. The methods determine topics for breakout rooms and their complexity scores. A breakout room is created for the topics, including separate breakout rooms for complex topics. An expertise score based on a plurality of factors for each device associated with a participant is also calculated. Devices are assigned to separate breakout rooms based on either just the expertise score or if the expertise score meets the threshold of the complexity score. Performance within the breakout rooms is displayed in real-time, such as in a graph. A moderator schedule is generated based the performance within the breakout rooms, where priority is given to a breakout room that has a negative performance over a breakout room with a positive performance.

Abstract: A power supply device communicable with a system and a method for supplying power to a system through a switch thereof are disclosed. The power supply device includes a switch, a microcontroller unit and a control circuit, and supplies power to the system through the switch. The microcontroller unit provides a first operating voltage to the switch through a first pin, and performs a firmware update procedure when the power supply device communicates with the system. The control circuit is coupled to the switch, and transmits a second operating voltage to the switch. When the microcontroller unit performs the firmware update procedure, the control circuit turns on the switch at least according to the second operating voltage, so that the power supply device does not stop supplying power to the system.

Abstract: TDD configuration may be dynamically and/or semi-statically signaled to user equipment devices by a base station. Semi-static TDD configuration may include: an initial portion for downlink transmission; a flexible portion; and a terminal portion for uplink transmission. TDD structure of the flexible portion may be determined later by transmission of dynamic physical layer configuration information such as downlink control information (DCI) and/or slot format indicator (SFI). (The SFI may be included in a group common PDCCH of a slot.) The downlink portion and/or the uplink portion may include subsets whose nominal transmit direction is subject to override by transmission of dynamic physical layer configuration information.

Abstract: Provided are a package structure and a method of forming the same. The method includes: laterally encapsulating a device die and an interconnect die by a first encapsulant; forming a redistribution layer (RDL) structure on the device die, the interconnect die, and the first encapsulant; bonding a package substrate onto the RDL structure, so that the RDL structure is sandwiched between the package substrate and the device die, the interconnect die, and the first encapsulant; laterally encapsulating the package substrate by a second encapsulant; and bonding a memory die onto the interconnect die, wherein the memory die is electrically connected to the device die through the interconnect die and the RDL structure.