Patents by Inventor Aalok Dyuti SAHA
Aalok Dyuti SAHA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11927624Abstract: One example includes a method for measuring a quiescent current in a switching voltage regulator. The method includes generating a mathematical model of a circuit design associated with the switching voltage regulator. The mathematical model includes measurable parameters to describe a switching current of a power switch of the switching voltage regulator. The method also includes fabricating a circuit comprising the switching voltage regulator based on the circuit design. The fabricated circuit includes the power switch and conductive I/O. The method also includes coupling the conductive I/O of the fabricated circuit to a circuit test fixture and providing electrical signals to the conductive I/O via the circuit test fixture. The method also includes measuring the measurable parameters in response to the electrical signals and applying the measurable parameters to the mathematical model to calculate the switching current.Type: GrantFiled: June 22, 2022Date of Patent: March 12, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Harsh Patel, Aalok Dyuti Saha, Sanjeev Praphulla Chandra Nyshadham, Subrato Roy, Gaurav Kumar Mittal
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Publication number: 20230417829Abstract: One example includes a method for measuring a quiescent current in a switching voltage regulator. The method includes generating a mathematical model of a circuit design associated with the switching voltage regulator. The mathematical model includes measurable parameters to describe a switching current of a power switch of the switching voltage regulator. The method also includes fabricating a circuit comprising the switching voltage regulator based on the circuit design. The fabricated circuit includes the power switch and conductive I/O. The method also includes coupling the conductive I/O of the fabricated circuit to a circuit test fixture and providing electrical signals to the conductive I/O via the circuit test fixture. The method also includes measuring the measurable parameters in response to the electrical signals and applying the measurable parameters to the mathematical model to calculate the switching current.Type: ApplicationFiled: June 22, 2022Publication date: December 28, 2023Inventors: HARSH PATEL, Aalok Dyuti Saha, Sanjeev Praphulla Chandra Nyshadham, Subrato Roy, Gaurav Kumar Mittal
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Publication number: 20230072953Abstract: One example includes a testing method that includes connecting a capacitor having a first capacitance to an output terminal of an integrated circuit (IC). The method can also include generating pulse signal responsive to an enable signal provided at at least one input terminal of the IC and providing a drive signal to the output terminal to cause a linearly increasing voltage across the capacitor responsive to the pulse signal. The method can also include measuring a no-load delay. The method can also include measuring the linearly increasing voltage at the output terminal responsive to the drive signal. The method can also include determining a first capacitance charge time for the capacitor responsive to the linearly increasing voltage reaching a threshold and determining a second capacitance charge delay for a second capacitance based on the first capacitance charge time and the no-load delay.Type: ApplicationFiled: August 19, 2022Publication date: March 9, 2023Inventors: Vasishta KIDAMBI, Harsh PATEL, Aalok Dyuti SAHA, Subrato ROY
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Publication number: 20230008179Abstract: In an example, a system includes a differential amplifier having a first input terminal and a second input terminal, the differential amplifier configured to be coupled to a boost diode of a boost converter. The system also includes an input diode coupled to the first input terminal and the second input terminal. The system includes a pull-up circuit coupled to the input diode and configured to be coupled to the boost diode. The system also includes a pull-down circuit coupled to the pull-up circuit. The system includes a transistor coupled to the pull-up circuit and the pull-down circuit.Type: ApplicationFiled: July 6, 2022Publication date: January 12, 2023Inventor: Aalok Dyuti SAHA
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Patent number: 11243235Abstract: A device includes a first transistor coupled to an input voltage source and to an output voltage node and an amplifier comprising a first input, a second input, and an output. The device also includes a second transistor coupled to the input voltage source and the first input of the amplifier and a third transistor coupled to the second transistor and a ground node. The third transistor includes a control terminal coupled to the output of the amplifier. The device also includes a first voltage-controlled voltage source coupled to a control terminal of the first transistor and a control terminal of the second transistor and a second voltage-controlled voltage source coupled to the first transistor and the second input of the amplifier.Type: GrantFiled: December 21, 2018Date of Patent: February 8, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Bhaskar Ramachandran, Kushal D. Murthy, Aalok Dyuti Saha
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Patent number: 10917058Abstract: A servo-amplifier includes a first bipolar transistor, a second bipolar transistor, a cascode transistor, and a bias transistor. The second bipolar transistor includes an emitter terminal that is connected to an emitter terminal of the first bipolar transistor to form a differential amplifier. The cascode transistor includes a source terminal that is connected to a collector terminal of the first bipolar transistor. The bias transistor is coupled to the first bipolar transistor, the second bipolar transistor and the cascode transistor. The bias transistor is configured to generate a bias voltage to drive a gate terminal of the cascode transistor based on a voltage at a base terminal of the first bipolar transistor and a voltage at a base terminal of the second bipolar transistor. As a result, neither of the bipolar transistors enters a saturation region during transient or steady state operation.Type: GrantFiled: November 9, 2018Date of Patent: February 9, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Aalok Dyuti Saha, Bhaskar Ramachandran
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Patent number: 10579082Abstract: An apparatus includes a power transistor to conduct a load current from a supply voltage node to an output node and a current sense circuit coupled to the power transistor. The current sense circuit generates a current sense current proportional to the load current. A temperature sense circuit is included to generate a temperature sense voltage proportional to the temperature of the power FET. A thermal limit circuit is coupled to the temperature sense circuit. A current limit circuit is coupled to the current sense circuit and to the thermal limit circuit. The current limit circuit generates a control signal on a current limit circuit output node. The control signal is responsive to the current sense current and to a first current from the thermal limit circuit. The current limit circuit output node is coupled to a control input of the power transistor.Type: GrantFiled: December 3, 2018Date of Patent: March 3, 2020Assignee: Texas Instruments IncorporatedInventors: Aalok Dyuti Saha, Bhaskar Ramachandran, Dattatreya Baragur Suryanarayana
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Publication number: 20200011906Abstract: A device includes a first transistor coupled to an input voltage source and to an output voltage node and an amplifier comprising a first input, a second input, and an output. The device also includes a second transistor coupled to the input voltage source and the first input of the amplifier and a third transistor coupled to the second transistor and a ground node. The third transistor includes a control terminal coupled to the output of the amplifier. The device also includes a first voltage-controlled voltage source coupled to a control terminal of the first transistor and a control terminal of the second transistor and a second voltage-controlled voltage source coupled to the first transistor and the second input of the amplifier.Type: ApplicationFiled: December 21, 2018Publication date: January 9, 2020Inventors: Bhaskar RAMACHANDRAN, Kushal D. MURTHY, Aalok Dyuti SAHA
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Publication number: 20200012304Abstract: An apparatus includes a power transistor to conduct a load current from a supply voltage node to an output node and a current sense circuit coupled to the power transistor. The current sense circuit generates a current sense current proportional to the load current. A temperature sense circuit is included to generate a temperature sense voltage proportional to the temperature of the power FET. A thermal limit circuit is coupled to the temperature sense circuit. A current limit circuit is coupled to the current sense circuit and to the thermal limit circuit. The current limit circuit generates a control signal on a current limit circuit output node. The control signal is responsive to the current sense current and to a first current from the thermal limit circuit. The current limit circuit output node is coupled to a control input of the power transistor.Type: ApplicationFiled: December 3, 2018Publication date: January 9, 2020Inventors: Aalok Dyuti SAHA, Bhaskar RAMACHANDRAN, Dattatreya BARAGUR SURYANARAYANA
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Publication number: 20200014347Abstract: A servo-amplifier includes a first bipolar transistor, a second bipolar transistor, a cascode transistor, and a bias transistor. The second bipolar transistor includes an emitter terminal that is connected to an emitter terminal of the first bipolar transistor to form a differential amplifier. The cascode transistor includes a source terminal that is connected to a collector terminal of the first bipolar transistor. The bias transistor is coupled to the first bipolar transistor, the second bipolar transistor and the cascode transistor. The bias transistor is configured to generate a bias voltage to drive a gate terminal of the cascode transistor based on a voltage at a base terminal of the first bipolar transistor and a voltage at a base terminal of the second bipolar transistor. As a result, neither of the bipolar transistors enters a saturation region during transient or steady state operation.Type: ApplicationFiled: November 9, 2018Publication date: January 9, 2020Inventors: Aalok Dyuti SAHA, Bhaskar RAMACHANDRAN