Abstract: An apparatus for testing an electronic circuit includes a clock scan chain input, a clock scan chain output, and a number of clock controllers connected in series in a clock scan chain between the clock scan chain input and the clock scan chain output. Each of the clock controllers includes an input, a bypass flip flop connected to the input, a number of clock control bit flip flops connected in series to an output of the bypass flip flop, a bypass multiplexer having a first input connected to an output of a last of the clock control bit flip flops and a second input connected to the output of the bypass flip flop, and a holding flip flop having an input connected to the output of the bypass flip flop and an output connected to a select input of the bypass multiplexer.

Abstract: An on-chip clock controller configured to control cross-domain paths using clock chain signals is disclosed. The on-chip clock controller includes a clock bits module configured to receive a clock chain signal and to output an enable signal based upon the clock chain signal. The on-chip clock controller also includes a clock gating module that is communicatively coupled to the clock bits module. The clock gating module is configured to receive a clock signal and to selectively output either a signal corresponding to the clock signal or a non-transitioning signal based upon the enable signal for operating a state storage module.