Patents by Inventor Aapo Varpula

Aapo Varpula has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220344561
    Abstract: According to an example aspect of the present invention, there is provided a detector comprising an optically absorbing membrane suspended over a cavity between the membrane and a substrate, the substrate comprised in the detector, and a thermoelectric transducer attaching the optically absorbing membrane over the cavity, wherein the optically absorbing membrane forms a contacting element between n-type and p-type thermoelectric elements of the thermoelectric transducer.
    Type: Application
    Filed: September 11, 2020
    Publication date: October 27, 2022
    Inventors: Aapo Varpula, Jonna Tiira, Kirsi Tappura, Grigoras Kestutis, Mika Prunnila
  • Patent number: 11402272
    Abstract: An absorber structure for a thermal detector, the absorber structure including edges defining a basic form, a plurality of first legs of electrically conducting material joined in an electrically conductive manner to form, between the edges of the absorber structure, a grid having openings, the first legs forming at least one continuous connection between the edges of the absorber structure; and a plurality of second legs of electrically conducting material joined in an electrically conductive manner to the first legs, wherein the second legs protrude from the first legs into the openings of the grid and terminate at points of termination located at a distance from adjacent first legs.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: August 2, 2022
    Assignee: Teknologian tutkimuskeskus VTT Oy
    Inventors: Kirsi Tappura, Aapo Varpula, Mika Prunnila
  • Publication number: 20210404880
    Abstract: An absorber structure for a thermal detector, the absorber structure including edges defining a basic form, a plurality of first legs of electrically conducting material joined in an electrically conductive manner to form, between the edges of the absorber structure, a grid having openings, the first legs forming at least one continuous connection between the edges of the absorber structure; and a plurality of second legs of electrically conducting material joined in an electrically conductive manner to the first legs, wherein the second legs protrude from the first legs into the openings of the grid and terminate at points of termination located at a distance from adjacent first legs.
    Type: Application
    Filed: October 30, 2019
    Publication date: December 30, 2021
    Applicant: Teknologian tutkimuskeskus VTT Oy
    Inventors: Kirsi TAPPURA, Aapo VARPULA, Mika PRUNNILA
  • Patent number: 11199455
    Abstract: A wafer-level integrated thermal detector comprises a first wafer and a second wafer (W1, W2) bonded together. The first wafer (W1) includes a dielectric or semiconducting substrate (100), a dielectric sacrificial layer (102) deposited on the substrate, a support layer (104) deposited on the sacrificial layer or the substrate, a suspended active element (108) provided within an opening (106) in the support layer, a first vacuum-sealed cavity (110) and a second vacuum-sealed cavity (106) on opposite sides of the suspended active element. The first vacuum-sealed cavity (110) extends into the sacrificial layer (102) at the location of the suspended active element (108). The second vacuum-sealed cavity (106) comprises the opening of the support layer (104) closed by the bonded second wafer.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: December 14, 2021
    Assignee: TEKNOLOGIAN TUTKIMUSKESKUS VTT OY
    Inventors: Aapo Varpula, Bin Guo
  • Publication number: 20200309603
    Abstract: A wafer-level integrated thermal detector comprises a first wafer and a second wafer (W1, W2) bonded together. The first wafer (W1) includes a dielectric or semiconducting substrate (100), a dielectric sacrificial layer (102) deposited on the substrate, a support layer (104) deposited on the sacrificial layer or the substrate, a suspended active element (108) provided within an opening (106) in the support layer, a first vacuum-sealed cavity (110) and a second vacuum-sealed cavity (106) on opposite sides of the suspended active element. The first vacuum-sealed cavity (110) extends into the sacrificial layer (102) at the location of the suspended active element (108). The second vacuum-sealed cavity (106) comprises the opening of the support layer (104) closed by the bonded second wafer.
    Type: Application
    Filed: August 31, 2018
    Publication date: October 1, 2020
    Inventors: Aapo VARPULA, Bin GUO
  • Patent number: 10495514
    Abstract: A method for producing a mirror plate for a Fabry-Perot interferometer includes providing a substrate, which includes silicon, implementing a semi-transparent reflective coating on the substrate, forming a passivated region in and/or on the substrate by etching a plurality of voids in the substrate, and by passivating the surfaces of the voids, forming a first sensor electrode on top of the passivated region, and forming a second sensor electrode supported by the substrate.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: December 3, 2019
    Assignee: TEKNOLOGIAN TUTKIMUSKESKUS VTT OY
    Inventors: Aapo Varpula, Mika Prunnila, Kestutis Grigoras
  • Patent number: 10088362
    Abstract: A mirror plate (100) for a Fabry-Perot interferometer (300) includes a substrate (50), which includes silicon (Si), a semi-transparent reflective coating (110) implemented on the substrate (50), a de-coupling structure (DC1) formed on the substrate (50), a first sensor electrode (G1a) formed on top of the de-coupling structure (DC1), and a second sensor electrode (G1b), wherein the de-coupling structure (DC1) includes an electrically insulating layer (60a), and a first stabilizing electrode (G0a), which is located between the first sensor electrode (G1a) and the substrate (50).
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: October 2, 2018
    Assignee: Teknologian tutkimuskeskus VTT Oy
    Inventors: Aapo Varpula, Christer Holmlund, Anna Rissanen
  • Publication number: 20180052049
    Abstract: A method for producing a mirror plate for a Fabry-Perot interferometer includes providing a substrate, which includes silicon, implementing a semi-transparent reflective coating on the substrate, forming a passivated region in and/or on the substrate by etching a plurality of voids in the substrate, and by passivating the surfaces of the voids, forming a first sensor electrode on top of the passivated region, and forming a second sensor electrode supported by the substrate.
    Type: Application
    Filed: March 8, 2016
    Publication date: February 22, 2018
    Applicant: Teknologian tutkimuskeskus VTT Oy
    Inventors: Aapo Varpula, Mika Prunnila, Kestutis Grigoras
  • Publication number: 20170350761
    Abstract: A mirror plate (100) for a Fabry-Perot interferometer (300) includes a substrate (50), which includes silicon (Si), a semi-transparent reflective coating (110) implemented on the substrate (50), a de-coupling structure (DC1) formed on the substrate (50), a first sensor electrode (G1a) formed on top of the de-coupling structure (DC1), and a second sensor electrode (G1b), wherein the de-coupling structure (DC1) includes an electrically insulating layer (60a), and a first stabilizing electrode (G0a), which is located between the first sensor electrode (G1a) and the substrate (50).
    Type: Application
    Filed: December 18, 2015
    Publication date: December 7, 2017
    Inventors: Aapo Varpula, Christer Holmlund, Anna Rissanen