Abstract: A MEMS electrostatic actuator comprises first and second opposing electrode arrangements, wherein at least one of the electrode arrangements is movable. A dielectric material (24) is adjacent the one of the electrode arrangements (22). The second electrode arrangement is patterned such that it includes electrode areas (26) and spaces adjacent the electrode areas, wherein the dielectric material (24) extends at least partially in or over the spaces. The invention uses a multitude of electrode portions as one plate. The electric field lines thus form clusters between the individual electrode portions and the opposing electrode. This arrangement provides an extended range of continuous actuation and tunability.

Abstract: The present invention relates to a method for fabricating an electronic component, comprising fabricating, on a substrate (102) at least one integrated MIM capacitor (114) having a top capacitor electrode (118) and a bottom capacitor electrode (112) at a smaller distance from the substrate than the top capacitor electrode; fabricating an electrically insulating first cover layer (120) on the top capacitor electrode, which first cover layer partly or fully covers the top capacitor electrode and is made of a lead-containing dielectric material; thinning the first cover layer; fabricating an electrically insulating second cover layer (124) on the first cover layer, which second cover layer partly or fully covers the first cover layer and has a dielectric permittivity smaller than that of the first cover layer; and fabricating an electrically conductive resistor layer (126) on the second cover layer, which resistor layer has a defined ohmic resistance.

Abstract: The present invention relates to an electronic component, that comprises, on a substrate, at least one integrated MIM capacitor, (114) an electrically insulating first cover layer (120) which partly or fully covers the top capacitor electrode (118) and is made of a lead-containing dielectric material, and a top barrier layer (122) on the first cover layer. The top barrier layer serves for avoiding a reduction of lead atoms comprised by the first cover layer under exposure of the first cover layer to a reducing substance. An electrically insulating second cover layer (124) on the top barrier layer has a dielectric permittivity smaller than that of the first cover layer establishes a low parasitic capacitance of the cover-layer structure. The described cover-layer structure with the intermediate top barrier layer allows to fabricate a high-accuracy resistor layer (126.1) on top.

Abstract: The invention relates to electronic device having an operation temperature range, wherein the electronic device comprises a tunable capacitor (CST) comprising a first electrode (BE), a second electrode (TE), and a dielectric (FEL) arranged between the first electrode (BE) and the second electrode (TE). The dielectric (FEL) comprises dielectric material (FEL) having a value of a relative dielectric constant (?r) varying at least within the operation temperature range. The electronic device further comprises a temperature varying means (RES) being thermally coupled to the tunable capacitor for providing a temperature of the dielectric (FEL) causing a predetermined capacitance of the tunable capacitor (CST). The invention, which relies on the idea of varying temperature to vary a capacitance of a capacitor stack, provides an alternative tunable capacitor type for the known types.

Abstract: The invention relates to a semiconductor device comprising a physical structure (50) for use in a physical unclonable function, wherein the physical structure (50) comprises a lead-zirconium titanate layer (25), and a silicon-comprising dielectric layer (27) deposited on the lead-zirconium-titanate layer (25), wherein the silicon-comprising dielectric layer (27) has a rough surface (SR), the physical structure (50) further comprising a conductive layer (30) provided on the rough surface (SR) of the silicon-comprising dielectric layer (27). The invention further relates to a method of manufacturing such semiconductor device. The invention also relates to a card, such as a smartcard, and to a RFID tag comprising such semiconductor device. The inventors have found that depositing of a silicon- comprising dielectric layer (27) on a lead-zirconium titanate layer (25) using vapor deposition results in a silicon-comprising dielectric layer (27) having a rough surface (SR).

Abstract: The present invention relates to an electric component comprising at least one first MIM capacitor having a ferroelectric insulator with a dielectric constant of at least 100 between a first capacitor electrode of a first electrode material and a second capacitor electrode of a second electrode material. The first and second electrode materials are selected such that the first MIM capacitor exhibits, as a function of a DC voltage applicable between the first and second electrodes, an asymmetric capacitance hysteresis that lets the first MIM capacitor, in absence of the DC voltage, assume one of at least two possible distinct capacitance values, in dependence on a polarity of a switching voltage last applied to the capacitor, the switching voltage having an amount larger than a threshold-voltage amount. The invention is applicable for ESD sensors, memories and high-frequency devices.

Abstract: A method of fabricating a trench capacitor, and a trench capacitor fabricated thereby, are disclosed. The method involves the use of a vacuum impregnation process for a sol-gel film, to facilitate effective deposition of high-permittivity materials within a trench in a semiconductor substrate, to provide a trench capacitor having a high capacitance while being efficient in utilization of semiconductor real estate.

Abstract: A capacitive ultrasound transducer includes a first electrode, a second electrode, and a third electrode, the third electrode including a central region disposed in collapsibly spaced relation with the first electrode, and a peripheral region disposed outward of the central region and disposed in collapsibly spaced relation with the second electrode. The transducer further includes a layer of a high dielectric constant material disposed between the third electrode and the first electrode, and between the third electrode and the second electrode. The transducer may be operable in a collapsed mode wherein the peripheral region of the third electrode oscillates relative to the second electrode, and the central region of the third electrode is fully collapsed with respect to the first electrode such that the dielectric layer is sandwiched therebetween. Piezoelectric actuation, such as d31 and d33 mode piezoelectric actuation, may further be included.

Abstract: A MEMS electrostatic actuator comprises first and second opposing electrode arrangements, wherein at least one of the electrode arrangements is movable. A dielectric material (24) is adjacent the one of the electrode arrangements (22). The second electrode arrangement is patterned such that it includes electrode areas (26) and spaces adjacent the electrode areas, wherein the dielectric material (24) extends at least partially in or over the spaces. The invention uses a multitude of electrode portions as one plate. The electric field lines thus form clusters between the individual electrode portions and the opposing electrode. This arrangement provides an extended range of continuous actuation and tunability.

Abstract: The present invention relates to a method for fabricating an electronic component, comprising fabricating, on a substrate (102) at least one integrated MIM capacitor (114) having a top capacitor electrode (118) and a bottom capacitor electrode (112) at a smaller distance from the substrate than the top capacitor electrode; fabricating an electrically insulating first cover layer (120) on the top capacitor electrode, which first cover layer partly or fully covers the top capacitor electrode and is made of a lead-containing dielectric material; thinning the first cover layer; fabricating an electrically insulating second cover layer (124) on the first cover layer, which second cover layer partly or fully covers the first cover layer and has a dielectric permittivity smaller than that of the first cover layer; and fabricating an electrically conductive resistor layer (126) on the second cover layer, which resistor layer has a defined ohmic resistance.

Abstract: The invention relates to a semiconductor device comprising a physical structure (50) for use in a physical unclonable function, wherein the physical structure (50) comprises a lead-zirconium titanate layer (25), and a silicon-comprising dielectric layer (27) deposited on the lead-zirconium-titanate layer (25), wherein the silicon-comprising dielectric layer (27) has a rough surface (SR), the physical structure (50) further comprising a conductive layer (30) provided on the rough surface (SR) of the silicon-comprising dielectric layer (27). The invention further relates to a method of manufacturing such semiconductor device. The invention also relates to a card, such as a smartcard, and to a RFID tag comprising such semiconductor device. The inventors have found that depositing of a silicon- comprising dielectric layer (27) on a lead-zirconium titanate layer (25) using vapor deposition results in a silicon-comprising dielectric layer (27) having a rough surface (SR).

Abstract: The present invention relates to an electronic component, that comprises, on a substrate, at least one integrated MIM capacitor, (114) an electrically insulating first cover layer (120) which partly or fully covers the top capacitor electrode (118) and is made of a lead-containing dielectric material, and a top barrier layer (122) on the first cover layer. The top barrier layer serves for avoiding a reduction of lead atoms comprised by the first cover layer under exposure of the first cover layer to a reducing substance. An electrically insulating second cover layer (124) on the top barrier layer has a dielectric permittivity smaller than that of the first cover layer establishes a low parasitic capacitance of the cover-layer structure. The described cover-layer structure with the intermediate top barrier layer allows to fabricate a high-accuracy resistor layer (126.1) on top.

Abstract: The present invention relates to an electric component comprising at least one first MIM capacitor having a ferroelectric insulator with a dielectric constant of at least 100 between a first capacitor electrode of a first electrode material and a second capacitor electrode of a second electrode material. The first and second electrode materials are selected such that the first MIM capacitor exhibits, as a function of a DC voltage applicable between the first and second electrodes, an asymmetric capacity hysteresis that lets the first MIM capacitor, in absence of the DC voltage, assume one of at least two possible distinct capacitance values, in dependence on a polarity of a switching voltage last applied to the capacitor, the switching voltage having an amount larger than a threshold-voltage amount. The invention is applicable for ESD sensors, memories and high-frequency devices.

Abstract: A method of fabricating a trench capacitor, and a trench capacitor fabricated thereby, are disclosed. The method involves the use of a vacuum impregnation process for a sol-gel film, to facilitate effective deposition of high-permittivity materials within a trench in a semiconductor substrate, to provide a trench capacitor having a high capacitance whilst being efficient in utilisation of semiconductor real estate.

Abstract: The invention relates to electronic device having an operation temperature range, wherein the electronic device comprises a tunable capacitor (CST) comprising a first electrode (BE), a second electrode (TE), and a dielectric (FEL) arranged between the first electrode (BE) and the second electrode (TE). The dielectric (FEL) comprises dielectric material (FEL) having a value of a relative dielectric constant (?r) varying at least within the operation temperature range. The electronic device further comprises a temperature varying means (RES) being thermally coupled to the tunable capacitor for providing a temperature of the dielectric (FEL) causing a predetermined capacitance of the tunable capacitor (CST). The invention, which relies on the idea of varying temperature to vary a capacitance of a capacitor stack, provides an alternative tunable capacitor type for the known types.

Abstract: A capacitive ultrasound transducer includes a first electrode, a second electrode, and a third electrode, the third electrode including a central region disposed in collapsibly spaced relation with the first electrode, and a peripheral region disposed outward of the central region and disposed in collapsibly spaced relation with the second electrode. The transducer further includes a layer of a high dielectric constant material disposed between the third electrode and the first electrode, and between the third electrode and the second electrode. The transducer may be operable in a collapsed mode wherein the peripheral region of the third electrode oscillates relative to the second electrode, and the central region of the third electrode is fully collapsed with respect to the first electrode such that the dielectric layer is sandwiched therebetween. Piezoelectric actuation, such as d31 and d33 mode piezoelectric actuation, may further be included.

Abstract: The invention relates to a method of manufacturing a semiconductor sensor device (10) for sensing a substance comprising a plurality of mutually parallel mesa-shaped semiconductor regions (1) which are formed on a surface of a semiconductor body (11) and which are connected at a first end to a first electrically conducting connection region (2) and at a second end to a second electrically conducting connection region (3) while a gas or a liquid comprising a substance to be sensed can flow between the mesa-shaped semiconductor regions (1) and the substance to be sensed can influence the electrical properties of the plurality of the mesa-shaped semiconductor regions (1), wherein at the surface of the semiconductor body (11) the first connection region (2) is formed and connected thereto with the first end the plurality of mesa-shaped semiconductor regions (1) is formed, and subsequently the second connection region (3) is formed connected to the plurality of mesa-shaped semiconductor regions (1) at their second