Abstract: An antenna structure is described that includes a flexible substrate and at least two antenna elements being formed from conductive traces on a layer of the flexible substrate. The antenna structure also includes a plurality of conductive traces formed on the layer of the flexible substrate with a first subset being electrically coupled as a lead in to a first one of the antenna elements and a second subset of the plurality of conductive traces being electrically coupled as a lead in to a second one of the antenna elements, wherein the first subset and the second subset are separately coupled electrically to one connector after insertion of an edge of the flexible substrate into the connector. An apparatus is described that includes a case, an electronic assembly, including a printed circuit board and a support bracket, contained within the case. The apparatus further includes the antenna assembly as described herein.

Abstract: A circuit for controlling wireless transmissions. The circuit includes a multi-input logic gate coupled to a power amplifier for wireless transmission. A first input of the logic gate is coupled to a first wireless transceiver; and a second input of the gate is coupled to one or more wireless devices.

Abstract: An ATSC (Advanced Television Systems Committee-Digital Television) receiver comprises an equalizer (220) and a lock detector (230). The equalizer (220) provides a sequence of received signal points (221) from a constellation space, the constellation space having an inner region and one, or more, outer regions. The lock detector (230) determines equalizer lock as a function of a noise power estimate developed from the number of received signal points falling in the one, or more, outer regions (305).

Abstract: A method and apparatus for generating the adaptive gain control signals in a communications receiver is disclosed. The present invention can be used with existing two stage gain architectures, and overcomes many undesirable characteristics of the previous mechanism. An apparatus is presented wherein each of a plurality of RF AGC gain controllable amplifiers are individually controlled by individual AGC control signals generated by an AGC controller so that the level of the output signal from each of the RF AGC gain controllable amplifiers is individually optimized for tuner performance.

Abstract: The present application generally relates to apparatuses such as television signal processing apparatus that process radio frequency signals. More specifically, the present application is particularly useful in integrated circuits that must combine circuitry operating in a synchronous-sampling mode that must be adapted for use with a fixed rate sampling mode application. According to an exemplary embodiment, the television signal processing apparatus comprises a source of a fixed rate digital signal, signal processing circuitry operating in a synchronous-sampling mode wherein the signal processing circuitry comprises a signal representing a symbol rate, and an interpolator for processing the fixed rate digital signal to yield samples at the symbol rate.

Abstract: Channel acquisition in a digital television signal receiver is improved by determining the carrier tracking loop frequency offsets and the symbol timing recovery offsets for each channel in the television receiver. Offsets are stored in respective EEPROMs for each channel. When a channel is to be acquired in the TV receiver the tune command will be applied to the appropriate EEPROMs and the respective values are conveyed to the VSB demodulator to start acquisition of the channel.

Abstract: A system is described for establishing timing synchronism between a local receiver symbol clock and a transmitter symbol clock. A prescribed number of offset values are calculated for desired symbol timing range, the offset values being grouped substantially symmetrically about a central offset value. Each of the preselected offset values are tested to see if symbol timing recovery lock can be achieved by starting at the central offset value and gradually moving away from such value. Finally, two timing detection algorithms are used and switched between the two algorithms is carried out as desired to maximize the possibility of STR lock.

Abstract: A software packet error system for a High Definition Television (HDTV) receiver. A data packet error signal is transferred from a forward error correcting Reed-Solomon decoder to a transport processor. In response to a segment sync signal, the transport processor generates an error signal which appears on a programmable output pin. The software packet error signal is synchronized with the outgoing data packet signal such that each data packet is bracketed or framed by its associating packet error signal. Precession of the start of the data packets forwarded on the transport but relative to the start of the data packets appearing at the output of the decoder occurs as a result of a training packet generated for every 312 data packets. The precession is reset at the beginning of every field and is predictable across the field duration with sufficient accuracy to make the software packet error mechanism feasible.