Patents by Inventor Aaron Buchwald

Aaron Buchwald has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250131443
    Abstract: A method and system for generating versions of assets comprising various levels of detail is provided. The method includes generating an institutional subnet with one or more blockchains. The method further includes enabling a set of administrative precompiles for the one or more blockchains, verifying whether a user of the institutional subnet is authorized to interact with the one or more blockchains. The method further includes generating a risk score associated with the user and modifying, based on the risk score, at least one administrative precompile in the set of administrative precompiles for the one or more blockchains based on risk score requirements of each of the blockchains.
    Type: Application
    Filed: December 12, 2024
    Publication date: April 24, 2025
    Inventor: Aaron Buchwald
  • Publication number: 20250069064
    Abstract: Various aspects of the subject technology relate to systems, methods, and machine-readable media for bridging native tokens. Various aspects may include initializing a first blockchain by allocating a plurality of native tokens. Aspects may also include transferring, using a bridge, one or more transactions from a second blockchain to the first blockchain using locked tokens on the second blockchain as collateral. Aspects may also include minting new native tokens at the first blockchain when a value of transactions sum to the plurality of native tokens and the plurality of native tokens are backed by the locked tokens. Aspects may also include reporting, to the second blockchain, the amount of tokens used for the transaction fees in the one or more transactions. Aspects may also include burning, at the second blockchain, tokens corresponding to the amount of tokens used for paying transaction fees.
    Type: Application
    Filed: August 22, 2024
    Publication date: February 27, 2025
    Inventors: Michael Kaplan, Patrick Robert O'Grady, Stephen Buttolph, Aaron Buchwald, Bernard Wong, Cameron John Schultz, Geoffrey Stuart, Matthew Lam
  • Publication number: 20250037120
    Abstract: Various aspects of the subject technology relate to systems, methods, and machine-readable media for cross-chain communication in a blockchain platform. Various aspects may include accepting, at a first blockchain, a first transaction including a message and a message payload. Aspects may also include validating, at the first blockchain, the message by signing the message using signature keys of one or more validators in a first set of validators of the first blockchain. Aspects may also include generating an aggregate signature based on the signature keys of the one or more validators in a first set of validators. Aspects may also include submitting a second transaction on to a second blockchain, the second transaction including the message and the aggregate signature. Aspects may include validating, at the second blockchain, the second transaction based on a shared registry.
    Type: Application
    Filed: October 8, 2024
    Publication date: January 30, 2025
    Inventors: Michael Edmond Kaplan, Stephen Buttolph, Daniel Laine, Alexander Dunn, Cameron John Schultz, Aaron Buchwald, Patrick Robert O'Grady, Bernard Wong
  • Publication number: 20240346507
    Abstract: A method and system for generating versions of assets comprising various levels of detail is provided. The method includes generating an institutional subnet with one or more blockchains. The method further includes enabling a set of administrative precompiles for the one or more blockchains, verifying whether a user of the institutional subnet is authorized to interact with the one or more blockchains. The method further includes generating a risk score associated with the user and modifying, based on the risk score, at least one administrative precompile in the set of administrative precompiles for the one or more blockchains based on risk score requirements of each of the blockchains.
    Type: Application
    Filed: October 20, 2023
    Publication date: October 17, 2024
    Inventor: Aaron Buchwald
  • Patent number: 12120246
    Abstract: Various aspects of the subject technology relate to systems, methods, and machine-readable media for cross-chain communication in a blockchain platform. Various aspects may include accepting, at a first blockchain, a first transaction including a message and a message payload. Aspects may also include validating, at the first blockchain, the message by signing the message using signature keys of one or more validators in a first set of validators of the first blockchain. Aspects may also include generating an aggregate signature based on the signature keys of the one or more validators in a first set of validators. Aspects may also include submitting a second transaction on to a second blockchain, the second transaction including the message and the aggregate signature. Aspects may include validating, at the second blockchain, the second transaction based on a shared registry.
    Type: Grant
    Filed: March 25, 2024
    Date of Patent: October 15, 2024
    Assignee: Ava Labs, Inc.
    Inventors: Michael Edmond Kaplan, Stephen Buttolph, Daniel Laine, Alexander Dunn, Cameron John Schultz, Aaron Buchwald, Patrick Robert O'Grady, Bernard Wong
  • Publication number: 20240333521
    Abstract: Various aspects of the subject technology relate to systems, methods, and machine-readable media for cross-chain communication in a blockchain platform. Various aspects may include accepting, at a first blockchain, a first transaction including a message and a message payload. Aspects may also include validating, at the first blockchain, the message by signing the message using signature keys of one or more validators in a first set of validators of the first blockchain. Aspects may also include generating an aggregate signature based on the signature keys of the one or more validators in a first set of validators. Aspects may also include submitting a second transaction on to a second blockchain, the second transaction including the message and the aggregate signature. Aspects may include validating, at the second blockchain, the second transaction based on a shared registry.
    Type: Application
    Filed: March 25, 2024
    Publication date: October 3, 2024
    Inventors: Michael Edmond Kaplan, Stephen Buttolph, Daniel Laine, Alexander Dunn, Cameron John Schultz, Aaron Buchwald, Patrick Robert O'Grady, Bernard Wong
  • Patent number: 11728817
    Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: August 15, 2023
    Assignee: MARVELL ASIA PTE LTD
    Inventors: Mrunmay Talegaonkar, Jorge Pernillo, Junyi Sun, Praveen Prabha, Chang-Feng Loi, Yu Liao, Jamal Riani, Belal Helal, Karthik S. Gopalakrishnan, Aaron Buchwald
  • Publication number: 20220190836
    Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.
    Type: Application
    Filed: January 3, 2022
    Publication date: June 16, 2022
    Inventors: Mrunmay TALEGAONKAR, Jorge PERNILLO, Junyi SUN, Praveen PRABHA, Chang-Feng LOI, Yu LIAO, Jamal RIANI, Belal HELAL, Karthik S. GOPALAKRISHNAN, Aaron BUCHWALD
  • Patent number: 11231741
    Abstract: The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a clock generator that includes a source clock generates a source clock signal at a low frequency. A clock multiplier multiplies the source clock signal by a predetermined factor to generate a high frequency clock signal. The high frequency clock signal is corrected by a time adjustment module by applying a compensation signal. The compensation signal is determined by a jitter measurement module, which uses both the high frequency clock signal and a jitter reference signal to determine the compensation signal. There are other embodiments as well.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: January 25, 2022
    Assignee: MARVELL ASIA PTE, LTD.
    Inventor: Aaron Buchwald
  • Patent number: 11218156
    Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: January 4, 2022
    Assignee: Marvell Asia Pte Ltd.
    Inventors: Mrunmay Talegaonkar, Jorge Pernillo, Junyi Sun, Praveen Prabha, Chang-Feng Loi, Yu Liao, Jamal Riani, Belal Helal, Karthik Gopalakrishnan, Aaron Buchwald
  • Publication number: 20200403627
    Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Inventors: Mrunmay TALEGAONKAR, Jorge PERNILLO, Junyi SUN, Praveen PRABHA, Chang-Feng LOI, Yu LIAO, Jamal RIANI, Belal HELAL, Karthik Gopalakrishnan, Aaron BUCHWALD
  • Patent number: 10804913
    Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: October 13, 2020
    Assignee: INPHI CORPORATION
    Inventors: Mrunmay Talegaonkar, Jorge Pernillo, Junyi Sun, Praveen Prabha, Chang-Feng Loi, Yu Liao, Jamal Riani, Belal Helal, Karthik Gopalakrishnan, Aaron Buchwald
  • Publication number: 20180131382
    Abstract: Systems and methods for converting analog signals to digital signals. A reference slice is associated with each of a plurality of active slices to balance the loading on an active sampling track and hold amplifier within each active slice. Alternatively, the reference slice is split into a portion having a reference ADC that is shared by a plurality of partial reference slices, each partial reference slice having a partial reference input module.
    Type: Application
    Filed: January 9, 2018
    Publication date: May 10, 2018
    Inventors: Josephus Van Engelen, Aaron Buchwald, Ralph Duncan
  • Patent number: 9866230
    Abstract: Systems and methods for converting analog signals to digital signals. A reference slice is associated with each of a plurality of active slices to balance the loading on an active sampling track and hold amplifier within each active slice. Alternatively, the reference slice is split into a portion having a reference ADC that is shared by a plurality of partial reference slices, each partial reference slice having a partial reference input module.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: January 9, 2018
    Assignee: Entropic Communications, LLC
    Inventors: Josephus Van Engelen, Aaron Buchwald, Ralph Duncan
  • Publication number: 20170111054
    Abstract: Systems and methods for converting analog signals to digital signals. A reference slice is associated with each of a plurality of active slices to balance the loading on an active sampling track and hold amplifier within each active slice. Alternatively, the reference slice is split into a portion having a reference ADC that is shared by a plurality of partial reference slices, each partial reference slice having a partial reference input module.
    Type: Application
    Filed: December 30, 2016
    Publication date: April 20, 2017
    Inventors: Josephus Van Engelen, Aaron Buchwald, Ralph Duncan
  • Patent number: 9537502
    Abstract: A system for calibrating time interleaved ADCs is disclosed and may include a time interleaved analog-to-digital converter (ADC) for converting analog signals to digital signals, the time interleaved ADC comprising: a plurality of active slices, and a plurality of reference slices, each reference slice associated with a corresponding one of the plurality of active slices. An output of each reference slice may be used to correct distortion in an output of the corresponding active slice. Each active slice may sample an input signal at a first rate and each associated reference slice may sample the input signal at a second rate, the second rate being slower than the first rate. Each sample taken by one of the plurality of reference slices may then be taken concurrent with a sample taken by the associated active slice. Each reference slice may include a reference sampling module and a dummy load.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: January 3, 2017
    Assignee: Entropic Communications, LLC
    Inventors: Josephus Van Engelen, Aaron Buchwald, Ralph Duncan
  • Publication number: 20160191071
    Abstract: A system for calibrating time interleaved ADCs is disclosed and may include a time interleaved analog-to-digital converter (ADC) for converting analog signals to digital signals, the time interleaved ADC comprising: a plurality of active slices, and a plurality of reference slices, each reference slice associated with a corresponding one of the plurality of active slices. An output of each reference slice may be used to correct distortion in an output of the corresponding active slice. Each active slice may sample an input signal at a first rate and each associated reference slice may sample the input signal at a second rate, the second rate being slower than the first rate. Each sample taken by one of the plurality of reference slices may then be taken concurrent with a sample taken by the associated active slice. Each reference slice may include a reference sampling module and a dummy load.
    Type: Application
    Filed: September 18, 2015
    Publication date: June 30, 2016
    Inventors: Josephus Van Engelen, Aaron Buchwald, Ralph Duncan
  • Publication number: 20150280725
    Abstract: Systems and methods for converting analog signals to digital signals. A reference slice is associated with each of a plurality of active slices to balance the loading on an active sampling track and hold amplifier within each active slice. Alternatively, the reference slice is split into a portion having a reference ADC that is shared by a plurality of partial reference slices, each partial reference slice having a partial reference input module.
    Type: Application
    Filed: July 2, 2014
    Publication date: October 1, 2015
    Inventors: Josephus van Engelen, Aaron Buchwald, Ralph Duncan
  • Patent number: 9143149
    Abstract: Systems and methods for converting analog signals to digital signals. A reference slice is associated with each of a plurality of active slices to balance the loading on an active sampling track and hold amplifier within each active slice. Alternatively, the reference slice is split into a portion having a reference ADC that is shared by a plurality of partial reference slices, each partial reference slice having a partial reference input module.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: September 22, 2015
    Assignee: Entropic Communications, LLC.
    Inventors: Josephus van Engelen, Aaron Buchwald, Ralph Duncan
  • Patent number: 8824538
    Abstract: Methods and systems adaptively equalizing an analog information signal, the method including sampling the analog information signal to provide analog samples including post-transition samples and steady-state samples, and equalizing the analog samples to produce equalized analog samples. The equalizing includes determining a difference between an average post-transition amplitude associated with at least one of the post-transition samples and an average steady-state amplitude associated with at least one of the steady-state samples, and adjusting an equalization coefficient to adjust the difference between the average post-transition amplitude and the average steady-state amplitude.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: September 2, 2014
    Assignee: Broadcom Corporation
    Inventors: Aaron Buchwald, Xicheng Jiang, Hui Wang, Howard A. Baumer, Avanindra Madisetti