Patents by Inventor Aaron C. Brown
Aaron C. Brown has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220162557Abstract: Provided herein are, inter alia, methods, compositions, and kits for producing adipocyte populations such as beige adipocyte populations. Also included are methods and compositions for increasing the level of adipocyte populations (e.g., beige adipocyte populations) in a subject, as well as methods and compositions for treating subjects who are overweight, obese, or who have diabetes.Type: ApplicationFiled: February 9, 2022Publication date: May 26, 2022Applicants: Maine Medical Center Research Institute, Maine Medical Center Research InstituteInventor: Aaron C. Brown
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Patent number: 11279915Abstract: Provided herein are, inter alia, methods, compositions, and kits for producing adipocyte populations such as beige adipocyte populations. Also included are methods and compositions for increasing the level of adipocyte populations (e.g., beige adipocyte populations) in a subject, as well as methods and compositions for treating subjects who are overweight, obese, or who have diabetes.Type: GrantFiled: January 11, 2019Date of Patent: March 22, 2022Assignee: Maine Medical Center Research InstituteInventor: Aaron C. Brown
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Publication number: 20190264178Abstract: Provided herein are, inter alia, methods, compositions, and kits for producing adipocyte populations such as beige adipocyte populations. Also included are methods and compositions for increasing the level of adipocyte populations (e.g., beige adipocyte populations) in a subject, as well as methods and compositions for treating subjects who are overweight, obese, or who have diabetes.Type: ApplicationFiled: January 11, 2019Publication date: August 29, 2019Inventor: Aaron C. Brown
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Patent number: 9594654Abstract: A method, system and computer-usable medium are disclosed for detecting the cause of a system hang in a verification environment. Hardware components associated with the design under test that are not included in the verification environment are replaced by software drivers. A dependency is set between a first driver and a second driver such that quiescing of the first driver is prevented until the second driver is quiesced. Each driver in a simulation test is designated to be either independent or dependent, with each dependent driver being associated with at least one independent driver. The independent driver is quiesced at a predetermined time. Dependent drivers do not quiesce until of their associated drivers have quiesced and completed all of their respectively issued instructions.Type: GrantFiled: December 24, 2013Date of Patent: March 14, 2017Assignee: International Business Machines CorporationInventors: Aaron C. Brown, David W. Cummings, Jeff J. Frankeny, Jonathan R. Jackson
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Patent number: 9507898Abstract: A computer identifies a storage element in a simulation model of an integrated circuit design that, during simulation of the integrated circuit design using the simulation model, is subject to having its value forced. In response to identifying the storage element, an indication of the storage element and the associated clock signal are stored in a database. In response to receiving an input indicating the value of the storage element is to be forced during simulation, a determination is made by reference to the database whether or not forcing of the value is mistimed with reference to the associated clock signal. In response to a determination that the forcing of the value as indicated by the input is mistimed with reference to the associated clock signal, an indication that forcing of the value is mistimed is output.Type: GrantFiled: December 6, 2013Date of Patent: November 29, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Santosh Balasubramanian, Aaron C. Brown, David W. Cummings, Ambalath Matayambath Roopesh
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Publication number: 20150178174Abstract: A method, system and computer-usable medium are disclosed for detecting the cause of a system hang in a verification environment. Hardware components associated with the design under test that are not included in the verification environment are replaced by software drivers. A dependency is set between a first driver and a second driver such that quiescing of the first driver is prevented until the second driver is quiesced. Each driver in a simulation test is designated to be either independent or dependent, with each dependent driver being associated with at least one independent driver. The independent driver is quiesced at a predetermined time. Dependent drivers do not quiesce until of their associated drivers have quiesced and completed all of their respectively issued instructions.Type: ApplicationFiled: December 24, 2013Publication date: June 25, 2015Applicant: International Business Machines CorporationInventors: Aaron C. Brown, David W. Cummings, Jeff J. Frankeny, Jonathan R. Jackson
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Publication number: 20140095141Abstract: A computer identifies a storage element in a simulation model of an integrated circuit design that, during simulation of the integrated circuit design using the simulation model, is subject to having its value forced. In response to identifying the storage element, an indication of the storage element and the associated clock signal are stored in a database. In response to receiving an input indicating the value of the storage element is to be forced during simulation, a determination is made by reference to the database whether or not forcing of the value is mistimed with reference to the associated clock signal. In response to a determination that the forcing of the value as indicated by the input is mistimed with reference to the associated clock signal, an indication that forcing of the value is mistimed is output.Type: ApplicationFiled: December 6, 2013Publication date: April 3, 2014Inventors: SANTOSH BALASUBRAMANIAN, AARON C. BROWN, DAVID W. CUMMINGS, AMBALATH MATAYAMBATH ROOPESH
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Publication number: 20130332137Abstract: A computer identifies a storage element in a simulation model of an integrated circuit design that, during simulation of the integrated circuit design using the simulation model, is subject to having its value forced. In response to identifying the storage element, an indication of the storage element and the associated clock signal are stored in a database. In response to receiving an input indicating the value of the storage element is to be forced during simulation, a determination is made by reference to the database whether or not forcing of the value is mistimed with reference to the associated clock signal. In response to a determination that the forcing of the value as indicated by the input is mistimed with reference to the associated clock signal, an indication that forcing of the value is mistimed is output.Type: ApplicationFiled: June 8, 2012Publication date: December 12, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Santosh Balasubramanian, Aaron C. Brown, David W. Cummings, Ambalath Matayambath Roopesh
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Patent number: 8396009Abstract: A network system supports multiple network communication protocols. In one embodiment, network device driver software provides a “Fibre Channel over Ethernet” communication capability and methodology. Device driver software manages a Fibre Channel to Ethernet and Ethernet to Fibre Channel address translation in real time for data packet communications in the network system. Different embodiments of the disclosed network system include multiple name servers and network device driver software that together provide multiple adapter name discovery methodologies. In one embodiment, the adapter name discovery methodologies include port name discovery and adapter attributes discovery.Type: GrantFiled: August 21, 2007Date of Patent: March 12, 2013Assignee: International Business Machines CorporationInventors: Aaron C. Brown, Scott M. Carlson, Kevin J. Gildea, Roger G. Hathorn, Jeffrey W. Palm, Renato J. Recio
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Patent number: 8359415Abstract: Mechanisms are provided for implementing a multi-root PCI manager (MR-PCIM) in a multi-root I/O virtualization management partition (MR-IMP) to control the shared functionality of an multi-root I/O virtualization (IOV) enabled switch fabric and multi-root IOV enabled I/O adapter (IOA) through the base functions (BF) of the switches and IOAs. A hypervisor provides device-independent facilities to the code running in the I/O Virtualization Management Partition (IMP), Multi-Root (MR)-IMP and client partitions. The MR-IMP may include device specific code without the hypervisor needing to sacrifice its size, robustness, and upgradeability. The hypervisor provides the virtual intermediary functionally for the sharing and control of the switch and IOA's control functions.Type: GrantFiled: May 5, 2008Date of Patent: January 22, 2013Assignee: International Business Machines CorporationInventors: Aaron C. Brown, Douglas M. Freimuth, Renato J. Recio, Steven M. Thurber
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Patent number: 8331381Abstract: A method of providing visibility of Ethernet components to a subnet manager in a converged InfiniBand over Ethernet (IBOE) network. If a port of an IBOE gateway corresponds to one or more InfiniBand devices, the subnet manager sends fabric management packets (FMPs) to discover the InfiniBand network and assigns physical local identifiers (LIDs) to the InfiniBand devices. If a port of the IBOE gateway corresponds to one or more Ethernet devices, the subnet manager sends FMPs to discover the Ethernet network. The subnet manager adds the Ethernet Media Access Control (MAC) addresses of any responding devices to an LID routing table and assigns LIDs to the Ethernet devices. The subnet manager configures one or more virtual Host Channel Adapters (HCAs) corresponding to the one or more Ethernet MAC addresses in the LID routing table.Type: GrantFiled: December 4, 2007Date of Patent: December 11, 2012Assignee: International Business Machines CorporationInventors: Aaron C. Brown, Jimmy R. Hill, Gregory F. Pfister, Renato J. Recio
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Patent number: 8310953Abstract: A network system supports multiple network communication protocols. In one embodiment, network device driver software provides a “Fiber Channel over Ethernet” communication capability and methodology. Device driver software manages a Fiber Channel to Ethernet and Ethernet to Fiber Channel address translation in real time for data packet communications in the network system. Different embodiments of the disclosed network system include multiple name servers and network device driver software that together provide multiple adapter name discovery methodologies. In one embodiment, the adapter name discovery methodologies include port name discovery and adapter attributes discovery.Type: GrantFiled: August 21, 2007Date of Patent: November 13, 2012Assignee: International Business Machines CorporationInventors: Aaron C. Brown, Scott M. Carlson, Kevin J. Gildea, Roger G. Hathorn, Jeffrey W. Palm, Renato J. Recio
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Patent number: 8307048Abstract: A network system supports multiple network communication protocols. An Ethernet component gateway in a Fiber Channel over Ethernet (FCoE) initiator system converts FCoE data packets from host devices to Fiber Channel over Internet Protocol (FCIP) data packets for transmission to a Storage Area Network (SAN) target system. The SAN target system may include a target Fiber Channel (FC) storage device and a SAN component gateway. The SAN component gateway converts FCIP data packets to SAN data packets for use by the target FC storage device. The SAN data packets may be either FC protocol data packets or FCoE protocol data packets. The SAN target system may provide for discovery of target FC storage device adapter information.Type: GrantFiled: July 15, 2008Date of Patent: November 6, 2012Assignee: International Business Machines CorporationInventors: Aaron C Brown, Scott M Carlson, Daniel G Eisenhauer, Roger G Hathorn, Jeffrey W Palm, Renato J Recio, Gregory J Tevis
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Patent number: 8165138Abstract: A method of providing a converged InfiniBand over Ethernet (IBOE) network. An IBOE switch receives a data packet. If the data packet is received by the IBOE switch from the InfiniBand network, a translation utility looks up an Ethernet media access control (MAC) address corresponding to an LID of the packet in a translation table. The translation utility generates an Ethernet packet and encapsulates an InfiniBand link layer packet before sending the packet. If the data packet is received by the IBOE switch from the Ethernet network, the translation utility removes the Ethernet header from the packet and looks up a LID corresponding to the MAC address. The translation utility calculates an outbound port number and sends the packet.Type: GrantFiled: December 4, 2007Date of Patent: April 24, 2012Assignee: International Business Machines CorporationInventors: Aaron C. Brown, Jimmy R. Hill, Gregory F. Pfister, Renato J. Recio
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Patent number: 8144582Abstract: Mechanisms for differentiating traffic types per host system blade in a multi-root PCI Express environment are provided. The mechanisms generate a first mapping data structure that, for each single-root virtual hierarchy in the multi-root data processing system, associates a plurality of traffic classes with a plurality of priority groups and maps each traffic class in the plurality of traffic classes to a corresponding virtual channel in a plurality of virtual channels. Moreover, a second mapping data structure is generated that maps each virtual channel in the plurality of virtual channels to corresponding per host system blade virtual links in a plurality of virtual links of the multi-root data processing system. Traffic of a particular priority group is routed from a single-root virtual hierarchy to a particular virtual link in the plurality of the virtual links based on the first mapping data structure and second mapping data structure.Type: GrantFiled: December 30, 2008Date of Patent: March 27, 2012Assignee: International Business Machines CorporationInventors: Aaron C. Brown, Douglas M. Freimuth, Renato J. Recio, Steven M. Thurber
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Patent number: 8141092Abstract: Mechanisms are provided for an I/O virtualization management partition (IMP) to control the shared functionality of an I/O virtualization (IOV) enabled I/O adapter (IDA) through a physical function (PF) of the IOA while the virtual functions (VFs) are assigned to client partitions for normal I/O operations directly. A hypervisor provides device-independent facilities to the code running in the IMP and client partitions. The IMP may include device specific code without the hypervisor needing to sacrifice its size, robustness, and upgradeability. The hypervisor provides the virtual intermediary functionally for the sharing and control of the IOA's control functions.Type: GrantFiled: November 15, 2007Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Aaron C. Brown, Douglas M. Freimuth, James A. Pafumi, Renato J. Recio, Steven M. Thurber
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Patent number: 8141093Abstract: Mechanisms that address the situation where an input/output (I/O) fabric is shared by more than one logical partition (LPAR) and where each LPAR can share with the other LPARs an I/O adapter (IOA) are provided. In particular, each LPAR is assigned its own separate address space to access a virtual function (VF) assigned to it such that each LPAR's perception is that it has its own independent IOA. Each VF may be shared across multiple LPARs. Facilities are provided for management of the shared resources of the IOA via a Physical Function (PF) of the IOA by assignment of that PF to an I/O Virtualization Management Partition (IMP). The code running in the IMP acts as a virtual intermediary to the VFs for fully managing the VF error handling, VF reset, and configuration operations. The IMP also acts as an interface to the PF for accessing common VF functionality.Type: GrantFiled: November 15, 2007Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Aaron C. Brown, Douglas M. Freimuth, Renato J. Recio, Steven M. Thurber
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Patent number: 8141094Abstract: Mechanisms to address the situation where an input/output (I/O) fabric is shared by more than one logical partition (LPAR) and where each LPAR can share with the other LPARs an I/O adapter (LOA) are provided. In particular, each LPAR is assigned its own separate address space to access a virtual function (VF) assigned to it such that each LPAR's perception is that it has its own independent IOA. Each VF may be shared across multiple LPARs. Facilities are provided for management of the shared resources of the IOA via a Physical Function (PF) of the IOA by assignment of that PF to an I/O Virtualization Management Partition (IMP). The code running in the IMP acts as a virtual intermediary to the VFs for fully managing the VF error handling, VF reset, and configuration operations. The IMP also acts as an interface to the PF for accessing common VF functionality.Type: GrantFiled: December 3, 2007Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Aaron C. Brown, Douglas M. Freimuth, Renato J. Recio, Steven M. Thurber
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Patent number: 8103810Abstract: Mechanisms for enabling both native and non-native input/output virtualization (IOV) in a single I/O adapter are provided. The mechanisms allow a system with a large number of logical partitions (LPARs) and system images to use IOV to share a native IOV enabled I/O adapter or endpoint that does not implement the necessary number of virtual functions (VFs) for each LPAR and system image. A number of VFs supported by the I/O adapter, less one, are assigned to LPARs and system images so that they may make use of native IOV using these VFs. The remaining VF is associated with a virtual intermediary (VI) which handles non-native IOV of the I/O adapter. Any remaining LPARs and system images share the I/O adapter using the non-native IOV via the VI. Thus, any number of LPARs and system images may share the same I/O adapter or endpoint.Type: GrantFiled: May 5, 2008Date of Patent: January 24, 2012Assignee: International Business Machines CorporationInventors: Aaron C. Brown, Douglas M. Freimuth, Renato J. Recio, Steven M. Thurber
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Patent number: 7941568Abstract: Registering memory space within a data processing system is performed. One or more open calls are received from an application to access one or more input/output (I/O) devices. Responsive to receiving the one or more open calls, one or more I/O map and pin calls are sent in order to register memory space for the one or more I/O devices within at least one storage area that will be accessed by the application. At least one virtual I/O bus address is received for each registered memory space of the one or more I/O devices. At least one I/O command is executed using the at least one virtual I/O bus address without intervention by an operating system or operating system image.Type: GrantFiled: May 5, 2008Date of Patent: May 10, 2011Assignee: International Business Machines CorporationInventors: Richard L. Arndt, Aaron C. Brown, Gregory F. Pfister, Renato J. Recio, Steven M. Thurber