Patents by Inventor Aaron CADAG

Aaron CADAG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190267311
    Abstract: The present disclosure is directed to leadless semiconductor packages with improved wettable flanks that encourage the formation of solder fillets when the leadless semiconductor package is mounted to a substrate. The solder fillets are consistently formed and are easily detectable by inspection systems, such as automated optical inspection (AOI) systems.
    Type: Application
    Filed: February 1, 2019
    Publication date: August 29, 2019
    Inventors: Ian Harvey ARELLANO, Aaron CADAG, Ela Mia CADAG
  • Publication number: 20190067212
    Abstract: A semiconductor package formed utilizing multiple etching steps includes a lead frame, a die, and a molding compound. The lead frame includes leads and a die pad. The leads and the die pad are formed from a first conductive material by the multiple etching steps. More specifically, the leads and the die pad of the lead frame are formed by at least three etching steps. The at least three etching steps including a first etching step, a second undercut etching step, and a third backside etching step. The second undercut etching step forming interlocking portions at an end of each lead. The end of the lead is encased in the molding compound. This encasement of the end of the lead with the interlocking portion allows the interlocking portion to mechanically interlock with the molding compound to avoid lead pull out. In addition, by utilizing at least three etching steps the leads can be formed to have a height that is greater than the die pad of the lead frame.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Inventors: Aaron Cadag., Lester Joseph Belalo., Ela Mia Cadag.
  • Publication number: 20190019745
    Abstract: A semiconductor package formed utilizing a removable backside protective layer includes a leadframe, a die pad, leads and a molding compound around them. The first surface of the die pad and leads are exposed to an external environment by the plurality of recesses. The recesses are formed by coupling a removable backside protective layer to the leadframe before applying the molding compound. After the molding compound is applied and cured, the backside protective layer is removed to expose the first surface of the die pad and the first surfaces of the leads so the semiconductor package may be mounted within an electronic device. The removable backside protective layer protects the die pad and the leads from mold flashing and residue when forming the semiconductor package during the fabrication process.
    Type: Application
    Filed: September 20, 2018
    Publication date: January 17, 2019
    Inventors: Aaron Cadag, Ian Harvey Arellano, Ela Mia Cadag
  • Publication number: 20180358286
    Abstract: The present disclosure is directed to a leadframe package having solder wettable sidewalls that is formed using a pre-molded leadframe and methods of manufacturing the same. A metal plated leadframe with a plurality of recesses and a plurality of apertures is placed into a top and bottom mold tool. A molding compound is then formed in the plurality of recesses and apertures in the leadframe to form a pre-molded leadframe. A plurality of die and wires are coupled to the pre-molded leadframe and the resulting combination is covered in an encapsulant. Alternatively, a bare leadframe can be processed and the metal layer can be applied after encapsulation. A saw or other cutting means is used for singulation to form leadframe packages. Each resulting leadframe package has a solder wettable sidewall for improving the strength of solder joints between the package and a circuit board.
    Type: Application
    Filed: August 21, 2018
    Publication date: December 13, 2018
    Inventors: Aaron CADAG, Ernesto ANTILANO, JR., Ela Mia CADAG
  • Publication number: 20180331020
    Abstract: A semiconductor package formed utilizing a removable backside protective layer includes a leadframe, a die pad, leads and a molding compound around them. The first surface of the die pad and leads are exposed to an external environment by the plurality of recesses. The recesses are formed by coupling a removable backside protective layer to the leadframe before applying the molding compound. After the molding compound is applied and cured, the backside protective layer is removed to expose the first surface of the die pad and the first surfaces of the leads so the semiconductor package may be mounted within an electronic device. The removable backside protective layer protects the die pad and the leads from mold flashing and residue when forming the semiconductor package during the fabrication process.
    Type: Application
    Filed: May 12, 2017
    Publication date: November 15, 2018
    Inventors: Aaron CADAG, Ian Harvey ARELLANO, Ela Mia CADAG
  • Patent number: 10128169
    Abstract: A semiconductor package formed utilizing a removable backside protective layer includes a leadframe, a die pad, leads and a molding compound around them. The first surface of the die pad and leads are exposed to an external environment by the plurality of recesses. The recesses are formed by coupling a removable backside protective layer to the leadframe before applying the molding compound. After the molding compound is applied and cured, the backside protective layer is removed to expose the first surface of the die pad and the first surfaces of the leads so the semiconductor package may be mounted within an electronic device. The removable backside protective layer protects the die pad and the leads from mold flashing and residue when forming the semiconductor package during the fabrication process.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: November 13, 2018
    Assignee: STMicroelectronics, Inc.
    Inventors: Aaron Cadag, Ian Harvey Arellano, Ela Mia Cadag
  • Patent number: 10079198
    Abstract: The present disclosure is directed to a leadframe package having solder wettable sidewalls that is formed using a pre-molded leadframe and methods of manufacturing the same. A metal plated leadframe with a plurality of recesses and a plurality of apertures is placed into a top and bottom mold tool. A molding compound is then formed in the plurality of recesses and apertures in the leadframe to form a pre-molded leadframe. A plurality of die and wires are coupled to the pre-molded leadframe and the resulting combination is covered in an encapsulant. Alternatively, a bare leadframe can be processed and the metal layer can be applied after encapsulation. A saw or other cutting means is used for singulation to form leadframe packages. Each resulting leadframe package has a solder wettable sidewall for improving the strength of solder joints between the package and a circuit board.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: September 18, 2018
    Assignee: STMicroelectronics, Inc.
    Inventors: Aaron Cadag, Ernesto Antilano, Jr., Ela Mia Cadag
  • Patent number: 9953933
    Abstract: A semiconductor package includes a substrate, a die, an insulating die attach film, a dummy die, a conductive layer, and an electrically conductive molding compound or encapsulant. The first surface of the substrate includes a plurality of internal leads, and the second surface of the substrate includes a plurality of external electrically conductive pads and an electrically conductive ground terminal. A non-conductive flow over wire die attach film is placed to surround and encase the die. The dummy die overlies the die and a conductive layer overlies the dummy die. The electrically conductive molding compound is formed to encase the various components of the semiconductor device. The electrically conductive molding compound is electrically coupled to the electrically conductive ground terminal and the conductive layer forming an EMI shield for the die in the package.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: April 24, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Aaron Cadag, Rennier Rodriguez, Ela Mia Cadag
  • Publication number: 20180016133
    Abstract: A MEMS pressure sensor packaged with a molding compound. The MEMS pressure sensor features a lead frame, a MEMS semiconductor die, a second semiconductor die, multiple pluralities of bonding wires, and a molding compound. The MEMS semiconductor die has an internal chamber, a sensing component, and apertures. The MEMS semiconductor die and the apertures are exposed to an ambient atmosphere. A method is desired to form a MEMS pressure sensor package that reduces defects caused by mold flashing and die cracking. Fabrication of the MEMS pressure sensor package comprises placing a lead frame on a lead frame tape; placing a MEMS semiconductor die adjacent to the lead frame and on the lead frame tape with the apertures facing the tape and being sealed thereby; attaching a second semiconductor die to the MEMS semiconductor die; attaching pluralities of bonding wires to form electrical connections between the MEMS semiconductor die, the second semiconductor die, and the lead frame; and forming a molding compound.
    Type: Application
    Filed: July 15, 2016
    Publication date: January 18, 2018
    Inventors: Aaron Cadag, Frederick Arellano, Ernesto Antilano, JR.
  • Publication number: 20150179477
    Abstract: A method of making packaged integrated circuit (IC) devices includes mixing a waste thermoset polymer material with a thermosetting polymer to form a mixed thermosetting polymer and packaging IC devices in a molding operation using the mixed thermosetting polymer to thereby recycle the waste thermoset polymer material. A packaged IC device includes an IC device and an encapsulating material surrounding the IC device. The encapsulating material includes a thermoset polymer matrix and thermoset polymer particles dispersed in thermoset polymer matrix.
    Type: Application
    Filed: December 23, 2013
    Publication date: June 25, 2015
    Applicant: STMicroelectronics, Inc.
    Inventors: AARON CADAG, BERNIE CHRISANTO ANG
  • Patent number: 9022773
    Abstract: A device and method for manufacturing integrated circuit packaging using a mold plunger with position compensation in a manufacturing setting. In an embodiment, a compensating mold plunger, which may be used during the manufacture of an integrated circuit package, engages a die set on a carrier and within a bushing. This may be done to inject a mold compound on top of the die/carrier. If the bushing that is housing the die/carrier tandem is misaligned with the plunger in any lateral direction, the amount of pressure may be compromised. A compensating mold plunger includes a flexible portion that allows for the head of the plunger to properly engage the die/carrier despite any possible misalignments. Further, different die/carrier combinations may also be used with a compensating mold plunger because the pressure and force applied may be uniform inside a bushing despite the contents of the bushing.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: May 5, 2015
    Assignee: STMicroelectronics, Inc.
    Inventors: Aaron Cadag, BernieChrisanto Ang, Richard Laylo
  • Publication number: 20130168898
    Abstract: A device and method for manufacturing integrated circuit packaging using a mold plunger with position compensation in a manufacturing setting. In an embodiment, a compensating mold plunger, which may be used during the manufacture of an integrated circuit package, engages a die set on a carrier and within a bushing. This may be done to inject a mold compound on top of the die/carrier. If the bushing that is housing the die/carrier tandem is misaligned with the plunger in any lateral direction, the amount of pressure may be compromised. A compensating mold plunger includes a flexible portion that allows for the head of the plunger to properly engage the die/carrier despite any possible misalignments. Further, different die/carrier combinations may also be used with a compensating mold plunger because the pressure and force applied may be uniform inside a bushing despite the contents of the bushing.
    Type: Application
    Filed: December 29, 2011
    Publication date: July 4, 2013
    Applicant: STMICROELECTRONICS ASIA PACIFIC PTE LTD.
    Inventors: Aaron CADAG, BernieChrisanto ANG, Richard LAYLO