Abstract: A configuration manager identifies a first device and a second device within a simulated system. Each device within the simulated system includes an inbound port and an outbound port. Next, the configuration manager injects a simulation only packet, at an “outbound time,” on the first device's outbound port and detects that the second device's inbound port receives the simulation only packet at an “inbound time.” As such, the configuration manager identifies a direct connection between the first device and the second device and computes a latency time for the connection. In turn, the configuration manager configures one or more first device configuration registers and one or more second device configuration registers based upon the computed latency time.

Abstract: A configuration manager identifies a first device and a second device within a simulated system. Each device within the simulated system includes an inbound port and an outbound port. Next, the configuration manager injects a simulation only packet on the first device's outbound port and detects that the second device's inbound port receives the simulation only packet. As a result, the configuration manager determines that a direct connection exists between the first device's outbound port and the second device's inbound port. In turn, the configuration manager configures one or more first device configuration registers and one or more second device configuration registers that correspond to the first device and the second device, respectively.

Abstract: A “LUN Table” enables Logical Unit Number (LUN) mapping/masking within an Input/Output Virtualization IOV adapter included in a Serial Attached Small Computer System Interface (“SAS” or “Serial Attached SCSI”). A plurality of System Images (“SI”) share block storage through the SAS. The IOV adapter includes one or more Virtual Functions (VF), a Physical Function (PF), and a LUN Table within the PF. The VF allows each SI to communicate I/0 requests with a storage device through the PF. The LUN Table maps the I/0 requests to unique locations within the storage device. Each SI is isolated from all other SIs. Interference between each SI is avoided. A VIOS or a LUN mapping/masking SAN are not required. I/0 latency, processor overhead and storage cost are improved over prior LUN mapping/masking solutions.

Abstract: When a hypervisor in a computer server receives input/output (I/O) data traffic, the hypervisor sends the I/O data traffic to a security sensor application shared by multiple operating system (OS) partitions. If the security sensor application indicates that the I/O data traffic meets pre-defined security standards in the security sensor application, and the I/O data traffic is addressed to one of the OS partitions in the computer server, the hypervisor sends the I/O data traffic to the applicable OS partition. If the I/O data traffic meets the pre-defined security standards, and the I/O data traffic is not addressed to one of the OS partitions, the hypervisor sends the I/O data traffic to an external destination in a network coupled to the computer server.

Abstract: A configuration manager identifies a first device and a second device within a simulated system. Each device within the simulated system includes an inbound port and an outbound port. Next, the configuration manager injects a simulation only packet on the first device's outbound port and detects that the second device's inbound port receives the simulation only packet. As a result, the configuration manager determines that a direct connection exists between the first device's outbound port and the second device's inbound port. In turn, the configuration manager configures one or more first device configuration registers and one or more second device configuration registers that correspond to the first device and the second device, respectively.

Abstract: A configuration manager identifies a first device and a second device within a simulated system. Each device within the simulated system includes an inbound port and an outbound port. Next, the configuration manager injects a simulation only packet, at an “outbound time,” on the first device's outbound port and detects that the second device's inbound port receives the simulation only packet at an “inbound time.” As such, the configuration manager identifies a direct connection between the first device and the second device and computes a latency time for the connection. In turn, the configuration manager configures one or more first device configuration registers and one or more second device configuration registers based upon the computed latency time.

Abstract: A “LUN Table” enables Logical Unit Number (LUN) mapping/masking within an IOV adapter included in a Serial Attached Small Computer System Interface (“SAS” or “Serial Attached SCSI”). A plurality of System Images (“SI”) share block storage through the SAS. The IOV adapter includes one or more Virtual Functions (VF), a Physical Function (PF), and a LUN Table within the PF. The VF allows each SI to communicate I/0 requests with a storage device through the PF. The LUN Table maps the I/0 requests to unique locations within the storage device. Each SI is isolated from all other SIs. Interference between each SI is avoided. A VIOS or a LUN mapping/masking SAN are not required. I/0 latency, processor overhead and storage cost are improved over prior LUN mapping/masking solutions.

Abstract: A method, computer program product and data processing system for verifying cumulative ordering. In one embodiment of the present invention a method comprises the step of selecting a memory barrier instruction issued by a particular processor. The method further comprises selecting a first cache line out of a plurality of cache lines to be paired with one or more of the remaining of the plurality of cache lines. If a load memory instruction executed after the memory barrier instruction in the first cache line was identified, then the first cache line selected will be paired with a second cache line. If a load memory instruction executed before the memory barrier instruction in the second cache line was identified, then a pair of load memory instructions has been identified. Upon identifying the second load memory instruction, a first and second reload of the first and second cache lines are identified.

Abstract: A method, computer program product and data processing system for verifying cumulative ordering. In one embodiment of the present invention a method comprises the step of selecting a memory barrier instruction issued by a particular processor. The method further comprises selecting a first cache line out of a plurality of cache lines to be paired with one or more of the remaining of the plurality of cache lines. If a load memory instruction executed after the memory barrier instruction in the first cache line was identified, then the first cache line selected will be paired with a second cache line. If a load memory instruction executed before the memory barrier instruction in the second cache line was identified, then a pair of load memory instructions has been identified. Upon identifying the second load memory instruction, a first and second reload of the first and second cache lines are identified.