Abstract: Systems, methods and computer program products assess processor performance metrics by monitoring probes constructed using instruction sequences. A first probe value can be determined from execution of a broad spectrum probe in an execution environment. In response to determining that the first probe value is not a first expected probe value, a targeted probe providing a second probe value directed to a subsystem of the execution environment, a feature of the subsystem, or a component of the execution environment is executed. In response to determining that the second probe value is not a second expected probe value, a differential between the second probe value and the second expected probe value can be used to determine that a bottleneck exists in at least one of the subsystem of the execution environment, the feature of the subsystem, or the component of the execution environment.

Abstract: Systems, methods and computer program products assess processor performance metrics by monitoring probes constructed using instruction sequences. A first probe value can be determined from execution of a broad spectrum probe in an execution environment. In response to determining that the first probe value is not a first expected probe value, a targeted probe providing a second probe value directed to a subsystem of the execution environment, a feature of the subsystem, or a component of the execution environment is executed. In response to determining that the second probe value is not a second expected probe value, a differential between the second probe value and the second expected probe value can be used to determine that a bottleneck exists in at least one of the subsystem of the execution environment, the feature of the subsystem, or the component of the execution environment.

Abstract: Systems, methods and computer program products assess processor performance metrics by monitoring probes constructed using instruction sequences. A first probe value can be determined from execution of a broad spectrum probe in an execution environment. In response to determining that the first probe value is not a first expected probe value, a targeted probe providing a second probe value directed to a subsystem of the execution environment, a feature of the subsystem, or a component of the execution environment is executed. In response to determining that the second probe value is not a second expected probe value, a differential between the second probe value and the second expected probe value can be used to determine that a bottleneck exists in at least one of the subsystem of the execution environment, the feature of the subsystem, or the component of the execution environment.

Abstract: Systems, methods and computer program products assess processor performance metrics by monitoring probes constructed using instruction sequences. A first probe value can be determined from execution of a broad spectrum probe in an execution environment. In response to determining that the first probe value is not a first expected probe value, a targeted probe providing a second probe value directed to a subsystem of the execution environment, a feature of the subsystem, or a component of the execution environment is executed. In response to determining that the second probe value is not a second expected probe value, a differential between the second probe value and the second expected probe value can be used to determine that a bottleneck exists in at least one of the subsystem of the execution environment, the feature of the subsystem, or the component of the execution environment.

Abstract: Processor performance metrics are assessed by monitoring probes constructed using instruction sequences. A probe comprising an instruction sequence is selected. The instruction sequence can be configured to measure at least one hardware metric. A first probe value is received. The first probe value can be based, at least in part, on the hardware metric. The first probe value can be determined from execution of the probe in a first execution environment. The probe can be executed a second time to determine a second probe value. The second probe value can be based, at least in part, on the hardware metric. The second probe value is determined in a second execution environment including at least one workload. The first probe value and the second probe value can be compared to produce a performance assessment of the second execution environment.

Abstract: Monitoring probes constructed using instruction sequences are used to assess processor performance metrics. A probe comprising an instruction sequence is selected. The instruction sequence can be configured to measure at least one hardware metric. A first probe value is received. The first probe value can be based, at least in part, on the hardware metric. The first probe value can be determined from execution of the probe in a first execution environment. The probe can be executed a second time to determine a second probe value. The second probe value can be based, at least in part, on the hardware metric. The second probe value is determined in a second execution environment including at least one workload. The first probe value and the second probe value can be compared to produce a performance assessment of the second execution environment.

Abstract: Processor performance metrics are assessed by monitoring probes constructed using instruction sequences. A probe comprising an instruction sequence is selected. The instruction sequence can be configured to measure at least one hardware metric. A first probe value is received. The first probe value can be based, at least in part, on the hardware metric. The first probe value can be determined from execution of the probe in a first execution environment. The probe can be executed a second time to determine a second probe value. The second probe value can be based, at least in part, on the hardware metric. The second probe value is determined in a second execution environment including at least one workload. The first probe value and the second. probe value can be compared to produce a performance assessment of the second execution environment.

Abstract: Monitoring probes constructed using instruction sequences are used to assess processor performance metrics. A probe comprising an instruction sequence is selected. The instruction sequence can be configured to measure at least one hardware metric. A first probe value is received. The first probe value can be based, at least in part, on the hardware metric. The first probe value can be determined from execution of the probe in a first execution environment. The probe can be executed a second time to determine a second probe value. The second probe value can be based, at least in part, on the hardware metric. The second probe value is determined in a second execution environment including at least one workload. The first probe value and the second probe value can be compared to produce a performance assessment of the second execution environment.

Abstract: In a computer system with a memory hierarchy, when a high-level cache supplies a data copy to a low-level cache, the shared copy can be either volatile or non-volatile. When the data copy is later replaced from the low-level cache, if the data copy is non-volatile, it needs to be written back to the high-level cache; otherwise it can be simply flushed from the low-level cache. The high-level cache can employ a volatile-prediction mechanism that adaptively determines whether a volatile copy or a non-volatile copy should be supplied when the high-level cache needs to send data to the low-level cache. An exemplary volatile-prediction mechanism suggests use of a non-volatile copy if the cache line has been accessed consecutively by the low-level cache. Further, the low-level cache can employ a volatile-promotion mechanism that adaptively changes a data copy from volatile to non-volatile according to some promotion policy, or changes a data copy from non-volatile to volatile according to some demotion policy.

Abstract: In a computer system with a memory hierarchy, when a high-level cache supplies a data copy to a low-level cache, the shared copy can be either volatile or non-volatile. When the data copy is later replaced from the low-level cache, if the data copy is non-volatile, it needs to be written back to the high-level cache; otherwise it can be simply flushed from the low-level cache. The high-level cache can employ a volatile-prediction mechanism that adaptively determines whether a volatile copy or a non-volatile copy should be supplied when the high-level cache needs to send data to the low-level cache. An exemplary volatile-prediction mechanism suggests use of a non-volatile copy if the cache line has been accessed consecutively by the low-level cache. Further, the low-level cache can employ a volatile-promotion mechanism that adaptively changes a data copy from volatile to non-volatile according to some promotion policy, or changes a data copy from non-volatile to volatile according to some demotion policy.

Abstract: In a computer system with a memory hierarchy, when a high-level cache supplies a data copy to a low-level cache, the shared copy can be either volatile or non-volatile. When the data copy is later replaced from the low-level cache, if the data copy is non-volatile, it needs to be written back to the high-level cache; otherwise it can be simply flushed from the low-level cache. The high-level cache can employ a volatile-prediction mechanism that adaptively determines whether a volatile copy or a non-volatile copy should be supplied when the high-level cache needs to send data to the low-level cache. An exemplary volatile-prediction mechanism suggests use of a non-volatile copy if the cache line has been accessed consecutively by the low-level cache. Further, the low-level cache can employ a volatile-promotion mechanism that adaptively changes a data copy from volatile to non-volatile according to some promotion policy, or changes a data copy from non-volatile to volatile according to some demotion policy.

Abstract: In a computer system with a memory hierarchy, when a high-level cache supplies a data copy to a low-level cache, the shared copy can be either volatile or non-volatile. When the data copy is later replaced from the low-level cache, if the data copy is non-volatile, it needs to be written back to the high-level cache; otherwise it can be simply flushed from the low-level cache. The high-level cache can employ a volatile-prediction mechanism that adaptively determines whether a volatile copy or a non-volatile copy should be supplied when the high-level cache needs to send data to the low-level cache. An exemplary volatile-prediction mechanism suggests use of a non-volatile copy if the cache line has been accessed consecutively by the low-level cache. Further, the low-level cache can employ a volatile-promotion mechanism that adaptively changes a data copy from volatile to non-volatile according to some promotion policy, or changes a data copy from non-volatile to volatile according to some demotion policy.

Abstract: A computer cache memory having at least two levels includes associativity sets allocated to congruence groups, each congruence group having multiple associativity sets (preferably two) in the higher level cache and multiple associativity sets (preferably three) in the lower level cache. The address range of an associativity set in the higher level cache is distributed among all the associativity sets in the lower level cache within the same congruence group, so that these lower level associativity sets are effectively shared by all associativity sets in the same congruence group in the higher level. The lower level cache is preferably a victim cache of the higher level cache. This sharing of lower level associativity sets by different associativity sets in the higher level effectively increases the associativity of the lower level to hold cast-outs of a hot associativity set in the upper level.