Abstract: Electronic device characterization platforms, systems, devices, and methods for use in testing instruments, devices, and sensors that is portable, modular, multiplexed, and automated are disclosed. The system includes a substrate, a chip adapter, such as a chip socket, and an optional housing. Chip samples to be tested can be disposed in the chip adapter and various environmental modules designed to supply different environmental conditions to the chip sample can be disposed over the chip adapter, enabling testing of the chip samples to be performed in the different environment conditions. The system can further include various connectors that allow for add-on modules to be included as part of the system. Methods of characterizing electronic devices and sensors are also disclosed.

Abstract: A fully-printed sensor chip for measuring prothrombin time of a blood sample. The sensor chip includes a pair of electrodes and a pair of contact pads, each electrically coupled to a different one of the electrodes, printed on the surface of the substrate using conductive ink materials. When a blood sample is placed on the sample chip in contact with both electrodes, an impedance of the blood sample is determined based on a measured impedance between the two contact pads. As the blood sample clots, the impedance value changes and the prothrombin time for the blood sample is determined based on a measurement time of a maximum impedance value. A resistive bridge printed on the substrate surface between the contact pads increases a baseline measurement for the sensor chip to a value within a range that is measurable by lower-cost measurement equipment.

Abstract: Electronic device characterization platforms, systems, devices, and methods for use in testing instruments, devices, and sensors that is portable, modular, multiplexed, and automated are disclosed. The system includes a substrate, a chip adapter, such as a chip socket, and an optional housing. Chip samples to be tested can be disposed in the chip adapter and various environmental modules designed to supply different environmental conditions to the chip sample can be disposed over the chip adapter, enabling testing of the chip samples to be performed in the different environment conditions. The system can further include various connectors that allow for add-on modules to be included as part of the system. Methods of characterizing electronic devices and sensors are also disclosed.

Abstract: Methods of measuring thickness of a material using cross-capacitance. The method generally includes applying a time-varying signal to a first pad and monitoring a response of a capacitor formed by the first pad, a spaced apart second pad, and the material. The pads may be permanently affixed to the material, in spaced relation to each other. Based on the response, a capacitance of the capacitor is determined. The material may be homogenous or heterogeneous, and has dielectric properties. Because the material acts as a dielectric, the capacitance of the capacitor changes as the thickness of the material changes. Thus, the thickness of the material may be determined based on the determined capacitance. The method may be advantageously employed to measure the thickness of a vehicle tire or other material. Related apparatuses are also disclosed.

Abstract: A metal structure including a first metal end region, a second metal end region, and an intermediate region between the first metal end region and the second metal end region, wherein the intermediate region comprises a metal nanostructure having a plurality of pores.

Abstract: Methods of forming an electrically conductive layer on a flexible substrate, such as a stretchable electrode, by aerosol jet printing on the flexible substrate while the substrate is strained. In general, a stretchable substrate is initially deformed so that a first surface thereof is under tension. While the substrate is in the strained state, an ink is aerosol jet printed onto the first surface. The ink includes carbon nanotubes, and advantageously other materials such as reduced graphene oxide. Further, while the substrate is still in the strained state, the ink is cured after its application to the substrate. Thereafter, the strain is decreased so that the stretchable substrate contracts, self-organizing into a configuration wherein the substrate's first surface, with the cured ink thereon, has a wrinkled profile. The flexible substrate can then be mechanically expanded and contracted, advantageously repeatedly, with the ink layer maintaining electrical conductivity.

Abstract: Methods of measuring thickness of a material using cross-capacitance. The method generally includes applying a time-varying signal to a first pad and monitoring a response of a capacitor formed by the first pad, a spaced apart second pad, and the material. The pads may be permanently affixed to the material, in spaced relation to each other. Based on the response, a capacitance of the capacitor is determined. The material may be homogenous or heterogeneous, and has dielectric properties. Because the material acts as a dielectric, the capacitance of the capacitor changes as the thickness of the material changes. Thus, the thickness of the material may be determined based on the determined capacitance. The method may be advantageously employed to measure the thickness of a vehicle tire or other material. Related apparatuses are also disclosed.

Abstract: A method of measuring thickness of a material generally includes transmitting an oscillating signal from a first pad, through the material, to a second pad, and measuring the signal reflected back to the first pad. The material may be homogenous or heterogeneous, and has dielectric properties. The signal has its frequency varied over time so that the frequency response of the system (the first pad, the material, and the second pad) may be analyzed. The resonant frequency of the system is determined. The thickness of the material is determined based on the resonant frequency shift caused by a change in thickness of the material. The present invention may be advantageously employed to measure the thickness of a vehicle tire or other material. Related apparatuses are also disclosed.

Abstract: Embodiments of the invention include a method of fabrication of a semiconductor structure. The method of fabrication includes: Forming a trench in a first dielectric material down to a first conductive material of a bottom gate. A sidewall of the trench contacts a top surface of the first conductive material. Depositing a second conductive material on the sidewall of the trench, which forms an electrical connection with the first conductive material. Depositing a second dielectric material in the trench, and on the second conductive material. Depositing a gate dielectric material on the second conductive material and the dielectric materials. Forming a channel material on the gate dielectric material. Depositing another conductive material on the channel material and portions of the gate dielectric material to form a source terminal and a drain terminal.

Abstract: A method of measuring thickness of a material generally includes transmitting an oscillating signal from a first pad, through the material, to a second pad, and measuring the signal reflected back to the first pad. The material may be homogenous or heterogeneous, and has dielectric properties. The signal has its frequency varied over time so that the frequency response of the system (the first pad, the material, and the second pad) may be analyzed. The resonant frequency of the system is determined. The thickness of the material is determined based on the resonant frequency shift caused by a change in thickness of the material. The present invention may be advantageously employed to measure the thickness of a vehicle tire or other material. Related apparatuses are also disclosed.

Abstract: In an aspect of the present invention, a graphene field-effect transistor (GFET) structure is formed. The GFET structure comprises a wider portion and a narrow extension portion extending from the wider portion that includes one or more graphene layers edge contacted to source and drain contacts, wherein the source and drain contacts are self-aligned to the one or more graphene layers.

Abstract: In an aspect of the present invention, a graphene field-effect transistor (GFET) structure is formed. The GFET structure comprises a wider portion and a narrow extension portion extending from the wider portion that includes one or more graphene layers edge contacted to source and drain contacts, wherein the source and drain contacts are self-aligned to the one or more graphene layers.

Abstract: A carbon nanotube semiconductor device includes at least one carbon nanotube disposed on an insulator portion of a substrate. The at least one carbon nanotube includes a non-doped channel portion interposed between a first doped source/drain portion and a second doped source/drain portion. A first source/drain contact stack is disposed on the first doped source/drain portion and an opposing second source/drain contact stack is disposed on the second doped source/drain portion. A replacement metal gate stack is interposed between the first and second source/drain contact stacks, and on the at least one carbon nanotube. The first and second doped source/drain portions are each vertically aligned with an inner edge of the first and second contact stacks, respectively.

Abstract: A carbon nanotube semiconductor device includes at least one carbon nanotube disposed on an insulator portion of a substrate. The at least one carbon nanotube includes a non-doped channel portion interposed between a first doped source/drain portion and a second doped source/drain portion. A first source/drain contact stack is disposed on the first doped source/drain portion and an opposing second source/drain contact stack is disposed on the second doped source/drain portion. A replacement metal gate stack is interposed between the first and second source/drain contact stacks, and on the at least one carbon nanotube. The first and second doped source/drain portions are each vertically aligned with an inner edge of the first and second contact stacks, respectively.

Abstract: A carbon nanotube semiconductor device includes at least one carbon nanotube disposed on an insulator portion of a substrate. The at least one carbon nanotube includes a non-doped channel portion interposed between a first doped source/drain portion and a second doped source/drain portion. A first source/drain contact stack is disposed on the first doped source/drain portion and an opposing second source/drain contact stack is disposed on the second doped source/drain portion. A replacement metal gate stack is interposed between the first and second source/drain contact stacks, and on the at least one carbon nanotube. The first and second doped source/drain portions are each vertically aligned with an inner edge of the first and second contact stacks, respectively.

Abstract: A carbon nanotube semiconductor device includes at least one carbon nanotube disposed on an insulator portion of a substrate. The at least one carbon nanotube includes a non-doped channel portion interposed between a first doped source/drain portion and a second doped source/drain portion. A first source/drain contact stack is disposed on the first doped source/drain portion and an opposing second source/drain contact stack is disposed on the second doped source/drain portion. A replacement metal gate stack is interposed between the first and second source/drain contact stacks, and on the at least one carbon nanotube. The first and second doped source/drain portions are each vertically aligned with an inner edge of the first and second contact stacks, respectively.

Abstract: In an aspect of the present invention, a graphene field-effect transistor (GFET) structure is formed. The GFET structure comprises a wider portion and a narrow extension portion extending from the wider portion that includes one or more graphene layers edge contacted to source and drain contacts, wherein the source and drain contacts are self-aligned to the one or more graphene layers.

Abstract: In one embodiment, SWNTs are synthesized from an embedded catalyst in a modified porous anodic alumina (PAA) template. Pd is electrodeposited into the template to form nanowires that grow from an underlying conductive layer beneath the PAA and extend to the initiation sites of the SWNTs within each pore. Individual vertical channels of SWNTs are created, each with a vertical Pd nanowire back contact. Further Pd deposition results in annular Pd nanoparticles that form on portions of SWNTs extending onto the PAA surface. Two-terminal electrical characteristics produce linear I-V relationships, indicating ohmic contact in the devices.

Abstract: In one embodiment, a multilayer graphene structure includes a first layer of graphene, a second layer of graphene; and an interstitial layer bonding the first layer of graphene to the second layer of graphene, wherein the interstitial layer comprises a polyaromatic compound. In another embodiment, a multilayer graphene structure is fabricated by providing a first layer of graphene, providing a second layer of graphene, and providing a first interstitial layer between the first layer of graphene and the second layer of graphene, wherein the first interstitial layer comprises a polyaromatic compound. In another embodiment, a multilayer graphene structure includes a plurality of layers of graphene and a plurality of interstitial layers formed of at least one polyaromatic compound, where each pair of the layers of graphene is bonded by one of the interstitial layers, such that a structure comprising alternating layers of graphene and interstitial layers is formed.

Abstract: In one embodiment, a multilayer graphene structure includes a first layer of graphene, a second layer of graphene; and an interstitial layer bonding the first layer of graphene to the second layer of graphene, wherein the interstitial layer comprises a polyaromatic compound. In another embodiment, a multilayer graphene structure is fabricated by providing a first layer of graphene, providing a second layer of graphene, and providing a first interstitial layer between the first layer of graphene and the second layer of graphene, wherein the first interstitial layer comprises a polyaromatic compound. In another embodiment, a multilayer graphene structure includes a plurality of layers of graphene and a plurality of interstitial layers formed of at least one polyaromatic compound, where each pair of the layers of graphene is bonded by one of the interstitial layers, such that a structure comprising alternating layers of graphene and interstitial layers is formed.