Abstract: An apparatus includes a register file including a logical circuit. The register file is configured to perform one or more logical operations in conjunction with the logical circuit. The logical operation is performed in response to the register file receiving a register file control instruction. The register file control instruction is independent from an arithmetic logic unit (ALU) control instruction and a multiply-and-accumulate unit (MACU) control instruction.

Abstract: An FSK receiver comprising: 1) demodulation circuitry for receiving an incoming FSK signal and generating a baseband signal comprising an amplitude modulated symbol stream, of Logic 0 symbols and Logic 1 symbols having a data rate, R; 2) auto-correlation circuitry for sampling the baseband signal S times during each symbol and generating an auto-correlation function comprising a sample stream of N-bit samples having a data rate, S×R, and having positive-going peaks approximately coinciding with the center of the Logic 1 symbol in a 010 sequence in the baseband signal and negative-going peaks approximately coinciding with the center of the Logic 0 symbols in a 101 sequence in the baseband signal; and 3) decision circuitry for receiving the auto-correlation function and deciding a logic level of a first symbol as a function of: 1) a comparison of a signal level of a center sample of the first symbol and a mean signal level of the auto-correlation function and 2) a comparison of the signal level of the center sa

Abstract: A radio frequency (RF) transceiver having improved low power operating modes. The RF transceiver comprises: 1) a radio frequency (RF) modem section comprising: a) receive path circuitry for receiving and down-converting an incoming RF signal to thereby produce an incoming baseband signal; and b) transmit path circuitry for receiving and up-converting an outgoing baseband signal to thereby produce an outgoing RF signal; 2) a baseband section comprising baseband circuitry for receiving and processing the incoming baseband signal and for generating the outgoing baseband signal; and 3) a power-saving apparatus for determining that the baseband section is idle and, in response to the determination, reducing a power supply voltage providing power to the baseband section.

Abstract: A signal detection circuit for receiving a digital baseband signal comprising an amplitude modulated symbol stream of Logic 0 symbols and Logic 1 symbols, each of the Logic 0 and Logic 1 symbols comprising S sequential samples, wherein the amplitude modulated symbol stream contains a preamble of N known symbols preceding a plurality of user data symbols. The signal detection circuit comprises: A) a signal mean determination circuit that receives G samples from the digital baseband signal and determines an amplitude mean value associated with the amplitude modulated symbol stream; and B) a correlation circuit that detects the preamble.

Abstract: An FSK receiver comprising: 1) demodulation circuitry for receiving an incoming FSK signal and generating a baseband signal comprising an amplitude modulated symbol stream of Logic 0 symbols and Logic 1 symbols having a data rate, R; 2) auto-correlation circuitry for sampling the baseband signal S times during each symbol and generating an auto-correlation function comprising a sample stream of N-bit samples having a data rate, S×R, and having positive-going peaks approximately coinciding with the center of the Logic 1 symbol in a 010 sequence in the baseband signal and negative-going peaks approximately coinciding with the center of the Logic 0 symbols in a 101 sequence in the baseband signal; and 3) decision circuitry for receiving the auto-correlation function and deciding a logic level of a first symbol as a function of: 1) a comparison of a signal level of a center sample of the first symbol and a mean signal level of the auto-correlation function and 2) a comparison of the signal level of the center sam