Patents by Inventor Aaron Daniels

Aaron Daniels has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210157735
    Abstract: A computer-implemented method, according to one approach, includes: determining a current read heat value of each logical page which corresponds to write requests that have accumulated in a destage buffer. Each of the write requests is assigned to a respective write queue based on the current read heat value of each logical page which corresponds to the write requests. Moreover, each of the write queues correspond to a different page stripe which includes physical pages, the physical pages included in each of the respective page stripes being of a same type. Other systems, methods, and computer program products are described in additional approaches.
    Type: Application
    Filed: February 3, 2021
    Publication date: May 27, 2021
    Inventors: Roman Alexander Pletka, Timothy Fisher, Aaron Daniel Fry, Nikolaos Papandreou, Nikolas Ioannou, Sasa Tomic, Radu Ioan Stoica, Charalampos Pozidis, Andrew D. Walls
  • Publication number: 20210138966
    Abstract: A retractable load carrier system for a vehicle comprising a rail assembly comprising a first rail and a second rail, wherein each rail is configured to be mounted to a vehicle roof. The system can further include a rack assembly comprising a first support member and a second support member generally parallel to each other, wherein the first support member and second support member can be coupled together with at least one cross members, wherein the rack assembly has a first end and a second end, wherein both the first and second end can include a handle portion. A locking means can be coupled to the handle portion of the rack assembly, wherein the locking means comprises a plurality of engagement members configured to latch to engage the grooved portion of the rail assembly or the pins are configured to engage the pinion portion of the rail assembly.
    Type: Application
    Filed: May 22, 2020
    Publication date: May 13, 2021
    Inventors: Aaron Daniels, Michael Boyle, Marc Scuiletti, Scott Daniels
  • Publication number: 20210134377
    Abstract: A computer-implemented method, according to one approach, includes: using a first calibration scheme to calibrate the given page in the block by calculating a first number of independent read voltage offset values for the given page. An attempt is made to read the calibrated given page, and in response to determining that an error correction code failure occurred when attempting to read the calibrated given page, a second calibration scheme is used to recalibrate the given page in the block. The second calibration scheme is configured to calculate a second number of independent read voltage offset values for the given page. An attempt to read the recalibrated given page is also made. In response to determining that an error correction code failure did occur when attempting to read the recalibrated given page, one or more instructions to relocate data stored in the given page are sent.
    Type: Application
    Filed: October 30, 2019
    Publication date: May 6, 2021
    Inventors: Nikolaos Papandreou, Charalampos Pozidis, Nikolas Ioannou, Roman Alexander Pletka, Radu Ioan Stoica, Sasa Tomic, Aaron Daniel Fry, Timothy Fisher
  • Publication number: 20210134378
    Abstract: A computer-implemented method, according to one approach, is for calibrating read voltages associated with a block of memory having more than one word-line therein. The computer-implemented method includes: for each of the word-lines in the block: calculating an absolute shift value for a reference read voltage associated with the given word-line. A relative shift value is also determined for each of the remaining read voltages associated with the given word-line, and the relative shift values are determined with respect to the reference read voltage. Moreover, each of the read voltages associated with the given word-line are adjusted using the absolute shift value and each of the respective relative shift values.
    Type: Application
    Filed: January 14, 2021
    Publication date: May 6, 2021
    Inventors: Nikolaos Papandreou, Charalampos Pozidis, Nikolas Ioannou, Roman Alexander Pletka, Radu Ioan Stoica, Sasa Tomic, Timothy Fisher, Aaron Daniel Fry
  • Publication number: 20210133070
    Abstract: A computer-implemented method, according to one embodiment, is for wear leveling blocks of memory. The computer-implemented method includes: determining the health of blocks of memory which are configured in multi-bit-per-cell mode. The blocks configured in multi-bit-per-cell mode are in a second pool, while blocks that are configured in single-level cell (SLC) mode are in a first pool. Moreover, the computer-implemented method is performed in some approaches with a proviso that the health of a block of memory is not determined while the block is configured in SLC mode. Moreover, health values are assigned to the blocks of memory in the second pool based on the health of the respective block. Each of the health values is further correlated with a respective data temperature.
    Type: Application
    Filed: October 30, 2019
    Publication date: May 6, 2021
    Inventors: Roman Alexander Pletka, Aaron Daniel Fry, Sasa Tomic, Nikolaos Papandreou, Nikolas Ioannou, Radu Ioan Stoica, Timothy Fisher
  • Publication number: 20210133110
    Abstract: A computer-implemented method, according to one embodiment, includes: determining whether a number of blocks included in a RTU queue associated with a first block pool is in a first predetermined range. In response to determining that the number of blocks included in the RTU queue is not in the first predetermined range, a determination is made as to whether a current I/O workload is in a second predetermined range. In response to determining that the current I/O workload is in the second predetermined range, for each block in the first block pool having a desired amount of metadata associated with the pages in the given block: a subset of pages in the given block are selected and data is relocated therefrom to a block in the second block pool.
    Type: Application
    Filed: October 30, 2019
    Publication date: May 6, 2021
    Inventors: Sasa Tomic, Radu Ioan Stoica, Nikolaos Papandreou, Nikolas Ioannou, Roman Alexander Pletka, Aaron Daniel Fry, Timothy Fisher
  • Publication number: 20210132800
    Abstract: A computer-implemented method, according to one embodiment, is for managing block calibration operations. The computer-implemented method includes: determining a type of calibration procedure to apply to a block of memory, and assigning the calibration type to the block. A calibration level to assign to the block is also determined, and thereafter the calibration level is assigned to the block. Moreover, the block is assigned to one of two or more calibration queues based on the calibration type and calibration level associated with the block. A different priority level is assigned to each of the calibration queues, and the priority levels determine an order in which blocks assigned to the calibration queues are calibrated.
    Type: Application
    Filed: October 30, 2019
    Publication date: May 6, 2021
    Inventors: Nikolaos Papandreou, Roman Alexander Pletka, Aaron Daniel Fry, Timothy Fisher, Nikolas Ioannou, Charalampos Pozidis, Radu Ioan Stoica, Sasa Tomic
  • Patent number: 10996078
    Abstract: Apparatus and associated methods relate to a linear variable differential transformer (LVDT) probe. The LVDT probe includes a plunger rod and a metal sheet formed into a cylinder with a C-shaped cross-section, the metal sheet configured to couple to the plunger rod. In an illustrative example, the coupling may be an interference fit aided by spring retention forces of the metal sheet. The metal sheet may be stamped, formed and applied to the plunger rod without annealing. In another example, the C-shaped metal sheet may be welded to the plunger rod at a distal and/or proximal end. The ratio of relative electromagnetic permeability of the metal sheet to the plunger rod may be greater than 10.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: May 4, 2021
    Assignee: HONEYWELL INTERNATIONAL INC.
    Inventor: Aaron Daniels
  • Publication number: 20210124488
    Abstract: A computer-implemented method, according to one embodiment, includes: maintaining a first subset of the plurality of blocks in a first pool, where the blocks maintained in the first pool are configured in SLC mode. A second subset of the plurality of blocks is maintained in a second pool, where the blocks maintained in the second pool are configured in multi-bit-per-cell mode. A current I/O rate for the memory is identified during runtime, and a determination is made as to whether the current I/O rate is outside a first range. In response to determining that the current I/O rate is not outside the first range, the blocks maintained in the first pool are used to satisfy incoming host writes. Moreover, in response to determining that the current I/O rate is outside the first range, the blocks maintained in the second pool are used to satisfy incoming host writes.
    Type: Application
    Filed: October 29, 2019
    Publication date: April 29, 2021
    Inventors: Radu Ioan Stoica, Roman Alexander Pletka, Timothy Fisher, Nikolaos Papandreou, Sasa Tomic, Nikolas Ioannou, Aaron Daniel Fry, Charalampos Pozidis, Andrew D. Walls
  • Publication number: 20210124643
    Abstract: A computer-implemented method, according to one embodiment, is for selectively storing parity data in different types of memory which include a higher performance memory and a lower performance memory. The computer-implemented method includes: receiving a write request, and determining whether the write request includes parity data. In response to determining that the write request includes parity data, a determination is made as to whether a write heat of the parity data is in a predetermined range. In response to determining that that write heat of the parity data is in the predetermined range, another determination is made as to whether the parity data has been read since a last time the parity data was updated. Furthermore, in response to determining that the parity data has been read since a last time the parity data was updated, the parity data is stored in the higher performance memory.
    Type: Application
    Filed: October 24, 2019
    Publication date: April 29, 2021
    Inventors: Nikolas Ioannou, Timothy Fisher, Roman Alexander Pletka, Nikolaos Papandreou, Radu Ioan Stoica, Sasa Tomic, Aaron Daniel Fry
  • Patent number: 10977181
    Abstract: A computer-implemented method, according to one approach, includes: receiving write requests, accumulating the write requests in a destage buffer, and determining a current read heat value of each logical page which corresponds to the write requests. Each of the write requests is assigned to a respective write queue based on the current read heat value of each logical page which corresponds to the write requests. Moreover, each of the write queues correspond to a different page stripe which includes physical pages, the physical pages included in each of the respective page stripes being of a same type. Furthermore, data in the write requests is destaged from the write queues to their respective page stripes. Other systems, methods, and computer program products are described in additional approaches.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: April 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Roman Alexander Pletka, Timothy Fisher, Aaron Daniel Fry, Nikolaos Papandreou, Nikolas Ioannou, Sasa Tomic, Radu Ioan Stoica, Charalampos Pozidis, Andrew D. Walls
  • Publication number: 20210098562
    Abstract: What is disclosed is structures and methods to integrate microdevices into system or receiver substrates. The integration of microdevices is facilitated by adding staging pads to microdevices before or after transferring. Creating stages after the transfer of a first microdevice to a substrate for the subsequent microdevice transfer to the first (or the second) microdevice transfer. The stage improves the surface profile of the substrate so that next microdevice can be transferred without the first microdevice on the substrate get damaged by or interfere with the surface of the donor or transfer head. Some embodiments further relate to tiled display device and more particularly, to stacking tiles to a backplane to form the tiled display device.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 1, 2021
    Applicant: VueReal Inc.
    Inventors: Gholamreza Chaji, Won Kyu Ha, Aaron Daniel Trent Wiersma, Ehsanollah Fathi
  • Patent number: 10955263
    Abstract: Apparatuses, systems, and associated methods of assembly are described that provide for improved sensor devices. An example sensor device includes a bobbin tube that defines a hollow interior. The device includes a primary coil element wound around the bobbin tube configured to, in response to a current input, generate a primary magnetic flux and includes a secondary coil element wound around the primary coil element. In an instance in which the bobbin tube receives a probe assembly therein, magnetic interaction between the probe assembly and the primary coil element is configured to induce a signal in the secondary coil element. Furthermore, a pitch of the secondary coil element varies according to a non-linear, polynomial function along a second length of the bobbin tube so as to reduce linearity error of the sensor device.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: March 23, 2021
    Assignee: Honeywell International Inc.
    Inventors: Subramanian Esakki, Aaron Daniels, Vijayshekhar Araganji
  • Patent number: 10957407
    Abstract: A computer-implemented method, according to one approach, is for calibrating read voltages for a block of memory. The computer-implemented method includes: determining a current operating state of a block which includes more than one word-line therein, and where more than one read voltage is associated with each of the word-lines. Moreover, for each of the word-lines in the block: one of the read voltages associated with the given word-line is selected as a reference read voltage, and an absolute shift value is calculated for the reference read voltage. A relative shift value is determined for each of the remaining read voltages associated with the given word-line, where the relative shift values are determined with respect to the reference read voltage. Furthermore, each of the read voltages associated with the given word-line are adjusted using the absolute shift value and each of the respective relative shift values.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Nikolaos Papandreou, Charalampos Pozidis, Nikolas Ioannou, Roman Alexander Pletka, Radu Ioan Stoica, Sasa Tomic, Timothy Fisher, Aaron Daniel Fry
  • Publication number: 20210065813
    Abstract: A computer-implemented method, according to one embodiment, includes: determining a current operating state of a block of memory. The block includes more than one type of page therein, and at least one read voltage is associated with each of the page types. The current operating state of the block is further used to produce a hybrid calibration scheme for the block which identifies a first subset of the read voltages, and a second subset of the read voltages. The read voltages in the second subset are further organized in one or more groupings. A unique read voltage offset value is calculated for each of the read voltages in the first subset, and a common read voltage offset value is also calculated for each grouping of read voltages in the second subset.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 4, 2021
    Inventors: Nikolaos Papandreou, Charalampos Pozidis, Nikolas Ioannou, Roman Alexander Pletka, Radu Ioan Stoica, Sasa Tomic, Timothy Fisher, Aaron Daniel Fry, Andrew D. Walls
  • Patent number: 10921446
    Abstract: Generally, a scanning device performs a sonic scan of a space by generating an ultrasonic impulse and measuring reflected signals as raw audio data. Sonic scan data including raw audio data and an associated scan location is forwarded to a sonic mapping service, which generates and distributes a 3D map of the space called a sonic map. When multiple devices contribute, the map is a collaborative sonic map. The sonic mapping service is advantageously available as distributed computing service, and can detect acoustic characteristics of the space and/or attribute visual/audio features to elements of a 3D model based on a corresponding detected acoustic characteristic. Various implementations that utilize a sonic map, detected acoustic characteristics, an impacted visual map, and/or an impacted 3D object include mixed reality communications, automatic calibration, relocalization, visualizing materials, rendering 3D geometry, and the like.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: February 16, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Jeffrey Ryan Sipko, Adolfo Hernandez Santisteban, Aaron Daniel Krauss, Priya Ganadas, Arthur C. Tomlin
  • Publication number: 20210042239
    Abstract: A computer-implemented method, according to one embodiment, is for maintaining heat information of data while in a cache. The computer-implemented method includes: transferring data from non-volatile memory to the cache, such that the data is stored in a first page in the cache. Previous read and/or write heat information associated with the data is maintained by preserving one or more bits in a hash table which correspond to the data in the first page. Moreover, the data is destaged from the first page in the cache to the non-volatile memory, and the one or more bits in the hash table which correspond to the data are updated to reflect current read and/or write heat information associated with the data.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Inventors: Nikolas Ioannou, Nikolaos Papandreou, Roman Alexander Pletka, Sasa Tomic, Radu Ioan Stoica, Timothy Fisher, Aaron Daniel Fry, Charalampos Pozidis, Andrew D. Walls
  • Publication number: 20210011852
    Abstract: A computer-implemented method, according to one approach, includes: receiving write requests, accumulating the write requests in a destage buffer, and determining a current read heat value of each logical page which corresponds to the write requests. Each of the write requests is assigned to a respective write queue based on the current read heat value of each logical page which corresponds to the write requests. Moreover, each of the write queues correspond to a different page stripe which includes physical pages, the physical pages included in each of the respective page stripes being of a same type. Furthermore, data in the write requests is destaged from the write queues to their respective page stripes. Other systems, methods, and computer program products are described in additional approaches.
    Type: Application
    Filed: July 10, 2019
    Publication date: January 14, 2021
    Inventors: Roman Alexander Pletka, Timothy Fisher, Aaron Daniel Fry, Nikolaos Papandreou, Nikolas Ioannou, Sasa Tomic, Radu Ioan Stoica, Charalampos Pozidis, Andrew D. Walls
  • Publication number: 20210004158
    Abstract: A computer-implemented method, according to one embodiment, includes: determining whether a number of blocks included in a first ready-to-use (RTU) queue is in a first range of the first RTU queue. In response to determining that the number of blocks included in the first RTU queue is in the first range, a determination is made as to whether a number of blocks included in a second RTU queue is in a second range of the second RTU queue. Moreover, in response to determining that the number of blocks included in the second RTU queue is not in the second range, valid data is relocated from one of the blocks in a first pool which corresponds to the first RTU queue. The block in the first pool is erased, and transferred from the first pool to the second RTU queue which corresponds to a second pool.
    Type: Application
    Filed: July 1, 2019
    Publication date: January 7, 2021
    Inventors: Roman Alexander Pletka, Radu Ioan Stoica, Sasa Tomic, Nikolaos Papandreou, Nikolas Ioannou, Aaron Daniel Fry, Timothy Fisher, Charalampos Pozidis, Andrew D. Walls
  • Publication number: 20210004159
    Abstract: A computer-implemented method, according to one embodiment, includes: maintaining a block switching metric for each block of memory in the storage system. A determination is made as to whether a first block in a first pool should be transferred to a second pool according to a block switching metric which corresponds to the first block. In response to determining that the first block in the first pool should be transferred to the second pool according to the block switching metric which corresponds to the first block, the first block is erased. The first block is then transferred from the first pool to a second RTU queue which corresponds to the second pool. A second block in the second pool is also erased and transferred from the second pool to a first RTU queue which corresponds to the first pool.
    Type: Application
    Filed: July 1, 2019
    Publication date: January 7, 2021
    Inventors: Roman Alexander Pletka, Aaron Daniel Fry, Timothy Fisher, Sasa Tomic, Nikolaos Papandreou, Nikolas Ioannou, Radu Ioan Stoica, Charalampos Pozidis, Andrew D. Walls