Abstract: A method for generating a design for a system implemented on a target device includes presenting a user with an interface that allows the user to weight objectives for an interconnect architecture of the design. The interconnect architecture is generated in response to weighted objectives provided by the user.

Abstract: Techniques for reducing latency in address decoding are described. According to one approach, a method of operating an addressing circuit comprises partitioning range of encoded addresses into a first and second subset of encoded addresses, sending a first encoded address to a address decode circuit from a controller. In response to determining that the first encoded address is contained in the first subset, decoding the first encoded address in a first duration. In response to determining that the first encoded address is contained in the second subset, decoding the first encoded address in a second duration which is longer than the first duration and simultaneously sending a halt signal to the controller to stop sending subsequent encoded addresses for decoding for the entirety of the second duration.

Abstract: A method for generating a design for a system implemented on a target device includes presenting a user with an interface that allows the user to weight objectives for an interconnect architecture of the design. The interconnect architecture is generated in response to weighted objectives provided by the user.

Abstract: Systems and methods for implementing tristate signaling are described. The systems include an integrated circuit that further includes a tristate system. The tristate system converts an encapsulated unidirectional signal into a tristate signal. A relation between multiple unidirectional signals and the tristate signal is established by encapsulating the unidirectional signals to represent the tristate signal. The establishment of the relation facilitates control of the tristate signal by controlling the encapsulated unidirectional signals.

Abstract: Methods and apparatus are provided for receiving performance constraints for implementing a system. A system tool receives constraints such as throughput, latency, power consumption, resource usage, etc. and generates an interconnection fabric using the constraint information. The interconnection fabric includes ports adapters used to connect master components and slave components. In some instances, port adapters and components are intelligently selected and connected using the constraint information.

Abstract: According to various embodiments, a programmable device assembly includes an FPGA coupled to a nonvolatile serial configuration memory (e.g., serial flash memory) and a volatile fast bulk memory (e.g., SRAM or SDRAM). The nonvolatile serial configuration memory contains both the FPGA configuration data and CPU instructions. When a predetermined condition occurs, a serial memory access component that is hard coded on the FPGA automatically reads the configuration data from the nonvolatile serial configuration memory. The configuration data is used to configure the FPGA with various components, including a CPU, a boot ROM with code for a boot copier, and a bus structure. When the CPU boots, code for the boot copier is executed so that the CPU instructions are copied from the nonvolatile serial configuration memory to the volatile fast bulk memory. The CPU then executes the CPU instructions stored in the volatile fast bulk memory.

Abstract: Mechanisms are provided to allow programmable chip systems to support parameter ranges or a parameter space instead of fixed parameters. A system parameter such as signal width, frequency, clock rate, may be accessed and changed at run-time instead of requiring regeneration and reimplementation of the programmable chip system. Optimized parameter values can be determined and used to generate a programmable chip system having fixed parameter values.

Abstract: According to various embodiments of the present invention, a programmable device assembly includes an FPGA coupled to a nonvolatile serial configuration memory (e.g., serial flash memory) and a volatile fast bulk memory (e.g., SRAM or SDRAM). The nonvolatile serial configuration memory contains both the FPGA configuration data and CPU instructions. When a predetermined condition occurs, a serial memory access component that is hard coded on the FPGA automatically reads the configuration data from the nonvolatile serial configuration memory. The configuration data is used to configure the FPGA with various components, including a CPU, a boot ROM with code for a boot copier, and a bus structure. When the CPU boots, code for the boot copier is executed so that the CPU instructions are copied from the nonvolatile serial configuration memory to the volatile fast bulk memory. The CPU then executes the CPU instructions stored in the volatile fast bulk memory.

Abstract: Methods and apparatus are provided for efficiently implementing a programmable chip using hardware description source files passed through multiple tools. A hardware description language source file is provided with mechanisms to allow tool-specific code to be handled by both a synthesis tool and by a simulation tool. Instructions are provided to direct a synthesis tool to read as code comments that a simulation tool is configured to disregard.

Abstract: Methods and apparatus are provided for embedding identification information on a programmable chip. Parameterizable components are selected for implementation on a programmable chip. Information relating to the parameterizable components is embedded on the programmable chip by storing the information using mechanisms such as look up tables associated with logic elements. Information can be used to identify types of components, versions of components, parameter sets, and other data associated with components implemented on the programmable device.

Abstract: Methods and apparatus are provided for testing logic, particularly arbitration logic on a programmable chip. Secondary components on a programmable chip are configured with delay mechanisms operable to pseudo-randomly delay responses to requests received using arbitration logic. Requests are typically generated by primary components. The delay mechanisms can be used to test the ability of a programmable chip system to handle a variety of secondary component wait-state and latency characteristics. The delay mechanism can also be used to improve system performance.

Abstract: Methods and apparatus are provided for implementing a bus arbitration priority encoding scheme with fairness. Bus arbitration logic is connected to multiple primary components or devices. The multiple primary components send requests to bus arbitration logic. The bus arbitration logic uses a request vector and an arbitration vector to determine a grant vector. The grant vector indicates what primary component should be allowed bus access.

Abstract: Methods and apparatus are provided for efficiently implementing a programmable chip using hardware description source files passed through multiple tools. A hardware description language source file is provided with mechanisms to allow tool-specific code to be handled by both a synthesis tool and by a simulation tool. Instructions are provided to direct a synthesis tool to read as code comments that a simulation tool is configured to disregard.