Patents by Inventor Aaron Foo

Aaron Foo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12235670
    Abstract: An embodiment may involve receiving a signal indicative of an edge of a reference clock, wherein the reference clock has a fixed clock period, wherein a hardware clock signal generator ticks at a variable clock period, and wherein a local time value is increased by a local time increment on ticks of the hardware clock signal generator; reading the local time value and writing it to a memory as a current time value; determining a difference between the current time value and a previous time value that was written to the memory in response to receiving a previous signal from the reference clock; based on the difference, determining an adjustment to the local time increment so that the local time value increases at a rate that is closer to that of the reference clock; and modifying the local time increment by the adjustment.
    Type: Grant
    Filed: February 12, 2024
    Date of Patent: February 25, 2025
    Assignee: FMAD Engineering (SNG) Pte. Ltd.
    Inventor: Aaron Foo
  • Patent number: 12184520
    Abstract: An example embodiment may involve obtaining a packet filter definition that specifies characteristics of packets; compiling the packet filter definition to instructions of low-level code; generating a hash template based on a subset of the instructions, wherein the hash template includes pairs of byte offsets and byte counts that define locations within the packets at which the characteristics are disposed; based on application of the hash template to a plurality of stored packets, creating hash table entries in a hash table, wherein the hash table entries are respectively associated with subsets of the stored packets, wherein the subsets of the stored packets have respectively unique patterns of values within their bytes at the locations defined by the pairs of byte offsets and byte counts; updating the hash table entries to refer to metadata relating to their respective subset of the stored packets; and storing the hash table and the metadata.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: December 31, 2024
    Assignee: FMAD ENGINEERING (SNG) PTE. LTD.
    Inventor: Aaron Foo
  • Patent number: 12036157
    Abstract: A support pad coupling mechanism for a surgical table extension unit and a surgical table are disclosed. The surgical table extension unit includes an extension adapter and a support pad. A lower side of the support pad is provided with two coupling plates that are perpendicular to the support pad. Each coupling plate is provided with a hook portion and a first position-limiting post. The first position-limiting posts extend along a direction perpendicular to the coupling plates. The extension adapter is provided with two second position-limiting posts that cooperate with the hook portions and two position-limiting recessed portions that cooperate with the first position-limiting posts. When the support pad and the extension adapter are coupled together, the first position-limiting posts are positioned in the position-limiting recessed portions and the hook portions are hooked onto the second position-limiting posts.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: July 16, 2024
    Assignee: Baxter Medical Systems GmbH + Co. KG
    Inventors: Debao Ma, Jipeng Wang, Qiang Hao, Aaron Foo, Guoxiang Wang
  • Publication number: 20240219954
    Abstract: An embodiment may involve receiving a signal indicative of an edge of a reference clock, wherein the reference clock has a fixed clock period, wherein a hardware clock signal generator ticks at a variable clock period, and wherein a local time value is increased by a local time increment on ticks of the hardware clock signal generator; reading the local time value and writing it to a memory as a current time value; determining a difference between the current time value and a previous time value that was written to the memory in response to receiving a previous signal from the reference clock; based on the difference, determining an adjustment to the local time increment so that the local time value increases at a rate that is closer to that of the reference clock; and modifying the local time increment by the adjustment.
    Type: Application
    Filed: February 12, 2024
    Publication date: July 4, 2024
    Inventor: Aaron Foo
  • Patent number: 11940835
    Abstract: An embodiment may involve receiving a signal indicative of an edge of a reference clock, wherein the reference clock has a fixed clock period, wherein a hardware clock signal generator ticks at a variable clock period, and wherein a local time value is increased by a local time increment on ticks of the hardware clock signal generator; reading the local time value and writing it to a memory as a current time value; determining a difference between the current time value and a previous time value that was written to the memory in response to receiving a previous signal from the reference clock; based on the difference, determining an adjustment to the local time increment so that the local time value increases at a rate that is closer to that of the reference clock; and modifying the local time increment by the adjustment.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: March 26, 2024
    Assignee: FMAD Engineering (SNG) Pte. Ltd.
    Inventor: Aaron Foo
  • Publication number: 20240053930
    Abstract: An embodiment may involve digital circuitry configured to: (i) receive a plurality of data packets, (ii) calculate, based on content at a pre-determined set of locations within the data packets, respective hash values for each of the data packets, and (iii) store, in a first memory, metadata containing the respective hash values; and a plurality of processors configured to: (i) read, from the first memory, the metadata, (ii) aggregate, based on the respective hash values, the metadata into flow statistics of flows defined by the data packets, and (iii) write, to a second memory, the flow statistics, wherein the flows are subsets of the data packets having common values in each of the pre-determined set of locations.
    Type: Application
    Filed: October 24, 2023
    Publication date: February 15, 2024
    Inventor: Aaron Foo
  • Patent number: 11836385
    Abstract: An embodiment may involve a network interface configured to capture data packets into a binary format and a non-volatile memory configured to temporarily store the data packets received by way of the network interface. The embodiment may also involve a first array of processing elements each configured to independently and asynchronously: (i) read a chunk of data packets from the non-volatile memory, (ii) identify flows of data packets within the chunk, and (iii) generate flow representations for the flows. The embodiment may also involve a second array of processing elements configured to: (i) receive the flow representations from the first array of processing elements, (ii) identify and aggregate common flows across the flow representations into an aggregated flow representation, (iii) based on a filter specification, remove one or more of the flows from the aggregated flow representation, and (iv) write information from the aggregated flow representation to the database.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: December 5, 2023
    Assignee: fmad engineering kabushiki gaisha
    Inventor: Aaron Foo
  • Publication number: 20230273638
    Abstract: An embodiment may involve receiving a signal indicative of an edge of a reference clock, wherein the reference clock has a fixed clock period, wherein a hardware clock signal generator ticks at a variable clock period, and wherein a local time value is increased by a local time increment on ticks of the hardware clock signal generator; reading the local time value and writing it to a memory as a current time value; determining a difference between the current time value and a previous time value that was written to the memory in response to receiving a previous signal from the reference clock; based on the difference, determining an adjustment to the local time increment so that the local time value increases at a rate that is closer to that of the reference clock; and modifying the local time increment by the adjustment.
    Type: Application
    Filed: February 25, 2022
    Publication date: August 31, 2023
    Inventor: Aaron Foo
  • Publication number: 20230269148
    Abstract: An example embodiment may involve obtaining a packet filter definition that specifies characteristics of packets; compiling the packet filter definition to instructions of low-level code; generating a hash template based on a subset of the instructions, wherein the hash template includes pairs of byte offsets and byte counts that define locations within the packets at which the characteristics are disposed; based on application of the hash template to a plurality of stored packets, creating hash table entries in a hash table, wherein the hash table entries are respectively associated with subsets of the stored packets, wherein the subsets of the stored packets have respectively unique patterns of values within their bytes at the locations defined by the pairs of byte offsets and byte counts; updating the hash table entries to refer to metadata relating to their respective subset of the stored packets; and storing the hash table and the metadata.
    Type: Application
    Filed: February 10, 2023
    Publication date: August 24, 2023
    Inventor: Aaron Foo
  • Patent number: 11704063
    Abstract: An embodiment may involve a network interface module; volatile memory configured to temporarily store data packets received from the network interface module; high-speed non-volatile memory; an interface connecting to low-speed non-volatile memory; a first set of processors configured to perform a first set of operations that involve: (i) reading the data packets from the volatile memory, (ii) arranging the data packets into chunks, each chunk containing a respective plurality of the data packets, and (iii) writing the chunks to the high-speed non-volatile memory; and a second set of processors configured to perform a second set of operations in parallel to the first set of operations, where the second set of operations involve: (i) reading the chunks from the high-speed non-volatile memory, (ii) compressing the chunks, (iii) arranging the chunks into blocks, each block containing a respective plurality of the chunks, and (iv) writing the blocks to the low-speed non-volatile memory.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: July 18, 2023
    Assignee: fmad engineering kabushiki gaisha
    Inventor: Aaron Foo
  • Patent number: 11681470
    Abstract: An embodiment may involve non-volatile memory configured to store chunks of data packets, wherein the chunks are associated with sequence numbers; a shared producer queue; one or more processors configured to transfer the chunks to the shared producer queue in order of the sequence numbers; an array of n sets of processors configured to: (i) read the chunks from the shared producer queue, (ii) re-write network addresses within the data packets to create modified chunks, and (iii) write the modified chunks to queues; and a field programmable gate array based network interface containing the queues and m physical ports, and configured to: (i) read the modified chunks in order of their sequence numbers, (ii) unpack the modified chunks into data packets, (iii) write updated checksums to the data packets, (iv) respectively select output ports for the data packets, and (v) transmit the data packets from the selected output ports.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: June 20, 2023
    Assignee: fmad engineering kabushiki gaisha
    Inventor: Aaron Foo
  • Publication number: 20220300213
    Abstract: An embodiment may involve a network interface configured to capture data packets into a binary format and a non-volatile memory configured to temporarily store the data packets received by way of the network interface. The embodiment may also involve a first array of processing elements each configured to independently and asynchronously: (i) read a chunk of data packets from the non-volatile memory, (ii) identify flows of data packets within the chunk, and (iii) generate flow representations for the flows. The embodiment may also involve a second array of processing elements configured to: (i) receive the flow representations from the first array of processing elements, (ii) identify and aggregate common flows across the flow representations into an aggregated flow representation, (iii) based on a filter specification, remove one or more of the flows from the aggregated flow representation, and (iv) write information from the aggregated flow representation to the database.
    Type: Application
    Filed: June 8, 2022
    Publication date: September 22, 2022
    Inventor: Aaron Foo
  • Patent number: 11392317
    Abstract: An embodiment may involve a network interface configured to capture data packets into a binary format and a non-volatile memory configured to temporarily store the data packets received by way of the network interface. The embodiment may also involve a first array of processing elements each configured to independently and asynchronously: (i) read a chunk of data packets from the non-volatile memory, (ii) identify flows of data packets within the chunk, and (iii) generate flow representations for the flows. The embodiment may also involve a second array of processing elements configured to: (i) receive the flow representations from the first array of processing elements, (ii) identify and aggregate common flows across the flow representations into an aggregated flow representation, (iii) based on a filter specification, remove one or more of the flows from the aggregated flow representation, and (iv) write information from the aggregated flow representation to the database.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: July 19, 2022
    Assignee: fmad engineering kabushiki gaisha
    Inventor: Aaron Foo
  • Patent number: 11249688
    Abstract: An embodiment may involve receiving a chunk and a chunk index, where the chunk contains packets captured by a network interface unit and the chunk index contains timestamps of first and last packets within the chunk. The chunk may be stored in a first ring buffer of a first memory and the chunk index may be stored in an index buffer of the first memory. A processor may allocate an entry in an I/O queue of a second memory and an entry in a chunk processing queue of the first memory. The processor may read the chunk processing queue to identify and copy the chunk from the first ring buffer to a location in a second ring buffer of the second memory, the location associated with the entry in the I/O queue. The same or a different processor may instruct a controller to write the chunk to a non-volatile memory unit.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: February 15, 2022
    Assignee: fmad engineering kabushiki gaisha
    Inventor: Aaron Foo
  • Publication number: 20210385308
    Abstract: An embodiment may involve executing a set of instructions, where the set of instructions define how to generate outputs that represent one or more data packets, and where segments of the outputs are copied from first parts of respective instructions in the set of instructions. The embodiment may further involve: retrieving, from a plurality of registers, a data packet header; retrieving, from the plurality of registers, a first part of a data packet payload and an increment value; applying the increment value to the first part of the data packet payload to generate a second part of the data packet payload; storing, in the plurality of registers, the first part of the data packet payload with the increment value applied; and providing, as additional segments of the outputs, the data packet header, the first part of the data packet payload, and the second part of the data packet payload.
    Type: Application
    Filed: August 19, 2021
    Publication date: December 9, 2021
    Inventor: Aaron Foo
  • Patent number: 11128740
    Abstract: An embodiment may involve executing a set of instructions, where the set of instructions define how to generate outputs that represent one or more data packets, and where segments of the outputs are copied from first parts of respective instructions in the set of instructions. The embodiment may further involve: retrieving, from a plurality of registers, a data packet header; retrieving, from the plurality of registers, a first part of a data packet payload and an increment value; applying the increment value to the first part of the data packet payload to generate a second part of the data packet payload; storing, in the plurality of registers, the first part of the data packet payload with the increment value applied; and providing, as additional segments of the outputs, the data packet header, the first part of the data packet payload, and the second part of the data packet payload.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: September 21, 2021
    Assignee: fmad engineering kabushiki gaisha
    Inventor: Aaron Foo
  • Publication number: 20210271423
    Abstract: An embodiment may involve a network interface module; volatile memory configured to temporarily store data packets received from the network interface module; high-speed non-volatile memory; an interface connecting to low-speed non-volatile memory; a first set of processors configured to perform a first set of operations that involve: (i) reading the data packets from the volatile memory, (ii) arranging the data packets into chunks, each chunk containing a respective plurality of the data packets, and (iii) writing the chunks to the high-speed non-volatile memory; and a second set of processors configured to perform a second set of operations in parallel to the first set of operations, where the second set of operations involve: (i) reading the chunks from the high-speed non-volatile memory, (ii) compressing the chunks, (iii) arranging the chunks into blocks, each block containing a respective plurality of the chunks, and (iv) writing the blocks to the low-speed non-volatile memory.
    Type: Application
    Filed: May 14, 2021
    Publication date: September 2, 2021
    Inventor: Aaron Foo
  • Publication number: 20210223997
    Abstract: An embodiment may involve non-volatile memory configured to store chunks of data packets, wherein the chunks are associated with sequence numbers; a shared producer queue; one or more processors configured to transfer the chunks to the shared producer queue in order of the sequence numbers; an array of n sets of processors configured to: (i) read the chunks from the shared producer queue, (ii) re-write network addresses within the data packets to create modified chunks, and (iii) write the modified chunks to queues; and a field programmable gate array based network interface containing the queues and m physical ports, and configured to: (i) read the modified chunks in order of their sequence numbers, (ii) unpack the modified chunks into data packets, (iii) write updated checksums to the data packets, (iv) respectively select output ports for the data packets, and (v) transmit the data packets from the selected output ports.
    Type: Application
    Filed: March 29, 2021
    Publication date: July 22, 2021
    Inventor: Aaron Foo
  • Patent number: 11036438
    Abstract: An embodiment may involve a network interface module; volatile memory configured to temporarily store data packets received from the network interface module; high-speed non-volatile memory; an interface connecting to low-speed non-volatile memory; a first set of processors configured to perform a first set of operations that involve: (i) reading the data packets from the volatile memory, (ii) arranging the data packets into chunks, each chunk containing a respective plurality of the data packets, and (iii) writing the chunks to the high-speed non-volatile memory; and a second set of processors configured to perform a second set of operations in parallel to the first set of operations, where the second set of operations involve: (i) reading the chunks from the high-speed non-volatile memory, (ii) compressing the chunks, (iii) arranging the chunks into blocks, each block containing a respective plurality of the chunks, and (iv) writing the blocks to the low-speed non-volatile memory.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: June 15, 2021
    Assignee: FMAD Engineering Kabushiki Gaisha
    Inventor: Aaron Foo
  • Publication number: 20210128385
    Abstract: A support pad coupling mechanism for a surgical table extension unit and a surgical table are disclosed. The surgical table extension unit includes an extension adapter and a support pad. A lower side of the support pad is provided with two coupling plates that are perpendicular to the support pad. Each coupling plate is provided with a hook portion and a first position-limiting post. The first position-limiting posts extend along a direction perpendicular to the coupling plates. The extension adapter is provided with two second position-limiting posts that cooperate with the hook portions and two position-limiting recessed portions that cooperate with the first position-limiting posts. When the support pad and the extension adapter are coupled together, the first position-limiting posts are positioned in the position-limiting recessed portions and the hook portions are hooked onto the second position-limiting posts.
    Type: Application
    Filed: November 5, 2020
    Publication date: May 6, 2021
    Inventors: Debao Martin MA, Jipeng WANG, Qiang HAO, Aaron FOO, Guoxiang WANG