Abstract: The present disclosure is generally directed to a method and apparatus to communicate data between two or more semiconductor devices. In an embodiment, a method includes synchronizing a master device with a slave device, where the master device includes a semiconductor device. Synchronizing includes transmitting a first synchronization marker data pattern via a first serial interface from the master device at a first time, and receiving a second synchronization marker data pattern via a second serial interface at the master device at a second time in response to transmitting the first synchronization marker data pattern. Synchronizing also includes determining, based at least in part on the first time and the second time, a third time when a reply is to be received by the master device in response to a request transmitted from the master device to the slave device.

Abstract: The present disclosure is generally directed to a method and apparatus to communicate data between two or more semiconductor devices. In an embodiment, a method includes synchronizing a master device with a slave device, where the master device includes a semiconductor device. Synchronizing includes transmitting a first synchronization marker data pattern via a first serial interface from the master device at a first time, and receiving a second synchronization marker data pattern via a second serial interface at the master device at a second time in response to transmitting the first synchronization marker data pattern. Synchronizing also includes determining, based at least in part on the first time and the second time, a third time when a reply is to be received by the master device in response to a request transmitted from the master device to the slave device.

Abstract: The present disclosure is generally directed to a method of communicating data between two or more semiconductor devices. Serial interfaces using the method have a reduction in latency compared to conventional serial interfaces. The method enables features needed for a serial interface, such as limited run lengths and recognizable data boundaries to establish alignment. In addition, a method for synchronizing two or more semiconductor devices through serial interfaces has been presented. This is done by passing a marker data pattern through the system.

Abstract: A memory device and system are disclosed that may include a serial data interface, a serial address interface, and a reference clock interface. The reference clock interface is configured to receive a signal from a reference clock source that provides a reference clock signal to a memory control device. The serial interfaces are coupled to other memory devices or memory control devices. A method of transferring data within a memory system using serial interfaces is also disclosed. The method includes performing clock multiplication on a reference clock to provide a multiplied clock, using the multiplied clock to serialize and transmit data onto a serial interface, recovering data from the seal interface, using the reference clock to determine an initial frequency for use by clock and data recovery module, using the data recovered from the serial interface to determine a phase and final frequency of a recovered clock, and using the recovered clock to de-serialize received serial data into parallel data words.

Abstract: The present disclosure is generally directed to a method of communicating data between two or more semiconductor devices. Serial interfaces using the method have a reduction in latency compared to conventional serial interfaces. The method enables features needed for a serial interface, such as limited run lengths and recognizable data boundaries to establish alignment. In addition, a method for synchronizing two or more semiconductor devices through serial interfaces has been presented. This is done by passing a marker data pattern through the system.

Abstract: A memory device and system are disclosed that may include a serial data interface, a serial address interface, and a reference clock interface. The reference clock interface is configured to receive a signal from a reference clock source that provides a reference clock signal to a memory control device. The serial interfaces are coupled to other memory devices or memory control devices. A method of transferring data within a memory system using serial interfaces is also disclosed. The method includes performing clock multiplication on a reference clock to provide a multiplied clock, using the multiplied clock to serialize and transmit data onto a serial interface, recovering data from the seal interface, using the reference clock to determine an initial frequency for use by clock and data recovery module, using the data recovered from the serial interface to determine a phase and final frequency of a recovered clock, and using the recovered clock to de-serialize received serial data into parallel data words.

Abstract: A method for channel bonding begins when a master transceiver receives a channel bonding sequence. The process continues with the master transceiver generating a channel bonding request and transmitting it and channel bonding configuration information to the slave transceiver. The process continues with each slave receiving the channel bonding sequence, the channel bonding request and the channel bonding configuration information. The process continues as each slave processes the channel bonding request and the channel bonding sequence in accordance with the channel bonding configuration information to determine individual slave channel bonding start information. The process continues as the master processes the channel bonding sequence in accordance with the channel bonding configuration information and the channel bonding request to determine master channel bonding start information.

Abstract: Framing transmit encoded output data begins by determining a scrambling remainder between scrambling of an input code word in accordance with a 1st scrambling protocol and the scrambling of the input code word in accordance with an adjustable scrambling protocol. The processing continues by adjusting the adjustable scrambling protocol based on the scrambling remainder to produce an adjusted scrambling protocol. The processing continues by scrambling the input code word in accordance with the 1st scrambling protocol to produce a 1st scrambled code word. The processing continues by scrambling the input code word in accordance with the adjusted scrambling protocol to produce a scrambled partial code word. The processing continues by determining a portion of the 1st scrambled code word based on the scrambling remainder. The process continues by combining the scrambled partial code word with the portion of the 1st scrambled code word to produce the transmit encoded output data.

Abstract: A programmable logic device includes a plurality of programmable multi-gigabit transceivers, programmable logic fabric, and a control module. Each of the plurality of programmable multi-gigabit transceivers is individually programmed to a desired transceiving mode of operation in accordance with a plurality of transceiver settings. The programmable logic fabric is operably coupled to the plurality of programmable multi-gigabit transceivers and is configured to process at least a portion of the data being transceived via the multi-gigabit transceivers. The control module is operably coupled to produce the plurality of transceiver settings based on a desired mode of operation for the programmable logic device.