Patents by Inventor Aaron Hurst

Aaron Hurst has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12099835
    Abstract: A system receives source code for analysis. The system identifies external references to reference code in source code. The reference code is not included in the source code received for analysis. The system generates code stubs corresponding to the external references. Each code stub describes a semantic context for the corresponding external reference. The system provides the set of source code and the one or more code stubs for analysis of the code, for example, using a code analysis tool.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: September 24, 2024
    Assignee: Black Duck Software, Inc.
    Inventors: Cameron Gunnin, Edward Moriarty, Aaron Hurst, Simon Fredrick Vicente Goldsmith
  • Patent number: 8438511
    Abstract: Methods, systems, and devices for logic synthesis that preserve a reset behavior of a circuit are provided. A method for logic synthesis may include providing the circuit. A memory element may be identified at a first location within the circuit, where the memory element is reset with a first reset value. The memory element may be relocated across a first portion of the circuit resulting in a one relocated memory element. The relocated memory element may be duplicated. The relocated memory element and the duplicated memory element may be connected with the circuit. Multiple reset values for the relocated memory element and the duplicated memory element may be determined, where the first reset value is produced at the first location when the multiple reset values are propagated through the circuit from the relocated memory element and the duplicated memory element to the first location.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: May 7, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventor: Aaron Hurst
  • Patent number: 8423939
    Abstract: Methods, systems, and machine-readable storage medium for logic synthesis that adjust a timing model of a circuit are provided. A first memory element from multiple memory elements of the circuit may be determined, where the first memory element is connected with a first portion of the circuit and is controlled by at least one first control signal. A combinational element within the first portion of the circuit may be determined. The combinational element may include at least one input or output coupled with a second memory element. The second memory element may be controlled by at least one second control signal. The second control signal may be incompatible with the first control signal. A first timing element may be inserted into the circuit at a location connecting the first timing element with the combinational element. A synthesis optimization may be performed utilizing the at least one first timing element.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: April 16, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventor: Aaron Hurst