Abstract: A non-transitory computer readable medium including instructions which, when executed by a processor, cause the processor to: store a design metric and a design metric variation from the simulation of the design metric for a subset of a plurality of conditions in an inner loop and an outer loop, wherein in the outer loop is a sample set of design dimensions and their respective values, while the inner loop varies a plurality of variation conditions of the subset; model the design metric and design metric variation using a response surface; and optimize the design metric or the design metric variation for the subset of a plurality of design dimensions using the response surface to generate an optimized design. In other aspects, a system and a method for design variation and optimization are provided.

Abstract: A non-transitory computer readable medium including instructions which, when executed by a processor, cause the processor to: store a design metric and a design metric variation from the simulation of the design metric for a subset of a plurality of conditions in an inner loop and an outer loop, wherein in the outer loop is a sample set of design dimensions and their respective values, while the inner loop varies a plurality of variation conditions of the subset; model the design metric and design metric variation using a response surface; and optimize the design metric or the design metric variation for the subset of a plurality of design dimensions using the response surface to generate an optimized design. In other aspects, a system and a method for design variation and optimization are provided.

Abstract: Systems and methods are described for simultaneously deriving an effective x-sigma corner for multiple, different circuit and/or process metrics for a semiconductor device. The result is an effective sigma that is representative of design intent. Some implementations account for covariance, and use joint probability as the criteria for the effective x-sigma corner (e.g., as opposed to a unique sigma level of each individual metric). Analysis results for each metric can be transformed to metric distributions in a common distribution framework, and a correlation matrix can be calculated. The transformed metric distributions can be input to a joint probability distribution set to achieve a target joint sigma level. The joint probability distribution and correlation matrix values can be used to back-calculate scaled x-sigma corners for each metric distribution. Simulation of the device can be performed at one or more of the scaled x-sigma corners.

Abstract: Systems and methods are described for simultaneously deriving an effective x-sigma corner for multiple, different circuit and/or process metrics for a semiconductor device. The result is an effective sigma that is representative of design intent. Some implementations account for covariance, and use joint probability as the criteria for the effective x-sigma corner (e.g., as opposed to a unique sigma level of each individual metric). Analysis results for each metric can be transformed to metric distributions in a common distribution framework, and a correlation matrix can be calculated. The transformed metric distributions can be input to a joint probability distribution set to achieve a target joint sigma level. The joint probability distribution and correlation matrix values can be used to back-calculate scaled x-sigma corners for each metric distribution. Simulation of the device can be performed at one or more of the scaled x-sigma corners.

Abstract: A method of optimizing MOSFET device production which includes defining key independent parameters, formulating those key independent parameters into a canonical variational form, calculating theoretical extracted parameters using at least one of key independent parameters in canonical variational form, physics-based analytical models, or corner models. The method also includes calculating simulated characteristics of a device using the key independent parameters and extracting target data parameters based on at least one of measured data and predicted data, comparing the simulated characteristics to the target data parameters, and modifying the theoretical extracted parameters or key independent parameters in canonical form as a result of the comparison. Then, calculating and outputting the simulated characteristics based on the modified theoretical extracted parameters and the modified key independent parameters in canonical form.

Abstract: A method of optimizing MOSFET device production which includes defining key independent parameters, formulating those key independent parameters into a canonical variational form, calculating theoretical extracted parameters using at least one of key independent parameters in canonical variational form, physics-based analytical models, or corner models. The method also includes calculating simulated characteristics of a device using the key independent parameters and extracting target data parameters based on at least one of measured data and predicted data, comparing the simulated characteristics to the target data parameters, and modifying the theoretical extracted parameters or key independent parameters in canonical form as a result of the comparison. Then, calculating and outputting the simulated characteristics based on the modified theoretical extracted parameters and the modified key independent parameters in canonical form.

Abstract: A system and method for deriving semiconductor manufacturing process corners using surrogate simulations is disclosed. The method may be used to determine individual performance metric yields, the number of out-of-specification conditions for a given number of simulation samples, and a total yield prediction for simultaneous multi-variable conditions. A surrogate simulation model, such as a Response Surface Model, may be generated from circuit simulation data or parametric data measurements and may be executed using a large number of multi-variable sample points to determine process corners defining yield limits for a device. The model may also be used to simulate process shifts and exaggerated input ranges for critical device parameters. In some embodiments, the derived process corners may better represent physically possible worst-case process corners than traditional general-purpose process corners, and may address differences in process sensitivities for individual circuits of the device.

Abstract: A system and method for deriving semiconductor manufacturing process corners using surrogate simulations is disclosed. The method may be used to determine individual performance metric yields, the number of out-of-specification conditions for a given number of simulation samples, and a total yield prediction for simultaneous multi-variable conditions. A surrogate simulation model, such as a Response Surface Model, may be generated from circuit simulation data or parametric data measurements and may be executed using a large number of multi-variable sample points to determine process corners defining yield limits for a device. The model may also be used to simulate process shifts and exaggerated input ranges for critical device parameters. In some embodiments, the derived process corners may better represent physically possible worst-case process corners than traditional general-purpose process corners, and may address differences in process sensitivities for individual circuits of the device.