Patents by Inventor Aaron J. Caffee

Aaron J. Caffee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10530368
    Abstract: A clock circuit includes a circuit configured to use a regulated voltage on a regulated voltage node to provide a frequency modulated clock signal having a frequency vacillating between a first frequency and a second frequency. The clock circuit includes an auxiliary loading circuit coupled to the regulated voltage node and configured to selectively provide load compensation for a load difference of the circuit. The load difference is a difference between a first load corresponding to the first frequency and a second load corresponding to the second frequency. The circuit may include a frequency divider circuit configured to use the regulated voltage on the regulated voltage node to generate the frequency modulated clock signal by frequency dividing an input clock signal according to a divide value vacillating between a first divide value and a second divide value.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: January 7, 2020
    Assignee: Silicon Laboratories Inc.
    Inventors: Aaron J. Caffee, Brian G. Drost
  • Publication number: 20200007136
    Abstract: A time-to-voltage converter is configured to generate an output voltage signal and a correlated reference voltage signal. The time-to-voltage converter includes a current source configured to generate a bias current through a current source output node. The time-to-voltage converter includes a first switched-capacitor circuit coupled to the current source output node and configured to generate the output voltage signal based on an input time signal and the bias current during a first interval. The time-to-voltage converter includes a second switched-capacitor circuit coupled to the current source output node and configured to generate the correlated reference voltage signal based on a reference time signal and the bias current during a second interval. The first interval and the second interval are non-overlapping intervals.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: Aaron J. Caffee, Jeffrey L. Sonntag, Brian G. Drost, Volodymyr Kratyuk
  • Publication number: 20200006314
    Abstract: An array of capacitors on an integrated circuit includes a plurality of unit capacitors. Each unit capacitor includes an isolated capacitor node formed in a pillar structure. Each unit capacitor further includes a shared capacitor adjacent to the isolated capacitor node. The shared capacitor node is electrically coupled to shared capacitor nodes of other unit capacitors in the array. Each unit capacitor further includes a shield node coupled to a low impedance node and formed adjacent to the isolated capacitor node to reduce the chance of capacitance forming between conductors to the isolated nodes and the shared nodes thereby preventing unwanted charge from entering the shared nodes and reducing linearity of the array.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 2, 2020
    Inventors: Aaron J. Caffee, Brian G. Drost
  • Publication number: 20200007138
    Abstract: A time-to-voltage converter includes a switched-capacitor circuit configured to charge an output node to a reset voltage level in a first interval of a conversion period and configured to shift a voltage on the output node from the reset voltage level to a shifted reset voltage level in a second interval of the conversion period. The time-to-voltage converter includes a current source selectively coupled to the output node. The current source is configured to provide a constant current to the output node in a third interval of the conversion period. The shifted reset voltage level is outside a voltage range defined by a first power supply voltage level on a first voltage reference node and a second power supply voltage level on a second voltage reference node.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 2, 2020
    Inventor: Aaron J. Caffee
  • Patent number: 10498352
    Abstract: A method for reducing data-dependent loading on a voltage reference pre-charges a capacitor of the capacitive digital-to-analog converter to configure the capacitor in a pre-charged state during a first interval. The method selectively discharges the capacitor from the pre-charged state according to a value of an input digital signal to configure the capacitor in a selectively discharged state during a second interval. The method holds an output node of the capacitive digital-to-analog converter at a reset voltage level during the first interval and the second interval. The output node is coupled to a first terminal of the capacitor. The method discharges any remaining charge on the capacitor and providing an output voltage signal to an output node of the capacitive digital-to-analog converter according to the selectively discharged state during a third interval. The output voltage signal has a voltage level corresponding to a value of the input digital signal.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: December 3, 2019
    Assignee: Silicon Laboratories Inc.
    Inventors: Aaron J. Caffee, Brian G. Drost, Volodymyr Kratyuk
  • Publication number: 20190305783
    Abstract: A clock generator includes an oscillator configured to generate an oscillating signal and a signal path configured to provide an output clock signal based on the oscillating signal. In response to a control signal, the clock generator is configured to neutralize periodic phase perturbations in the oscillating signal using opposing periodic phase perturbations. The neutralization may occur in the signal path. The signal path may be responsive to the control signal to adjust at least one of a duty cycle, a rise time, and a fall time of the output clock signal to cause alternating phase perturbations of the periodic phase perturbations to apply as the opposing periodic phase perturbations in the output clock signal. The neutralization may occur in the oscillator. The clock generator may include an auxiliary path configured to provide an auxiliary signal to the oscillator.
    Type: Application
    Filed: April 3, 2018
    Publication date: October 3, 2019
    Inventors: Aaron J. Caffee, Russell Croman, Brian G. Drost
  • Patent number: 10355642
    Abstract: A technique for reducing series resistance of an inductor system, which may increase the quality factor of the inductor system, has been disclosed. An apparatus includes a conductive loop formed from a first conductive layer. The conductive loop comprises a first terminal and a second terminal. The first terminal includes at least one first conductive finger in the first conductive layer. The second terminal includes at least one second conductive finger in the first conductive layer. The at least one second conductive finger is interdigitated with the at least one first conductive finger without directly contacting the at least one first conductive finger. The apparatus may include a serpentine gap in the first conductive layer. The apparatus may include at least one first conductive via coupled to a second conductive layer and coupled the at least one first conductive fingers, respectively.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: July 16, 2019
    Assignee: Silicon Laboratories Inc.
    Inventor: Aaron J. Caffee
  • Patent number: 10296026
    Abstract: A low-noise voltage reference generator that utilizes internal gain and feedback to generate an output signal having reduced sensitivity to power supply variations and loading conditions is described. A method includes generating a current based on a voltage drop across a resistor. The voltage drop is based on a second voltage drop across a gate terminal of a transistor and a source terminal of the transistor. The method includes the current using a reference voltage to generate a mirrored current through a node coupled to the drain terminal of the transistor. The method includes generating a level-shifted voltage using a voltage on the node. The method includes buffering the level-shifted voltage using a power supply voltage to generate the reference voltage.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: May 21, 2019
    Assignee: Silicon Laboratories Inc.
    Inventors: Aaron J. Caffee, Vaibhav Karkare
  • Patent number: 10254176
    Abstract: An apparatus includes a thermistor having a variable resistance with a first dependence on absolute temperature. The apparatus includes a reference resistor having a resistance with a second dependence on absolute temperature, the second dependence being less than or having opposite polarity to the first dependence. The reference resistor includes a switched-capacitor circuit. The apparatus includes a node coupled between the thermistor and the reference resistor. The node is configured to provide a signal indicative of absolute temperature based on the variable resistance and the reference resistance. The signal may be strain-invariant, proportional to a reference voltage, and indicative of a ratio of the variable resistance to the reference resistance. The apparatus may include a feedback circuit configured to maintain the node at a predetermined voltage level.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: April 9, 2019
    Assignee: Silicon Laboratories Inc.
    Inventors: Aaron J. Caffee, Jeffrey L. Sonntag
  • Patent number: 10153084
    Abstract: A technique for forming an integrated circuit including an inductor reduces magnetic coupling between the inductor and surrounding elements. The technique includes deliberate placement of circuit elements (e.g., terminals, pins, routing traces) in locations on the integrated circuit relative to a magnetic vector potential associated with the inductor and relative to a magnetic flux density field associated with the inductor to reduce or eliminate induced signals that degrade system performance.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: December 11, 2018
    Assignee: Silicon Laboratories Inc.
    Inventors: Aaron J. Caffee, Brian G. Drost
  • Patent number: 10044383
    Abstract: A technique that reduces or eliminates trading-off power amplifier efficiency and costly external filtering in amplitude and phase modulated sinusoidal signal generation uses multi-phase outphasing and a multi-phase switching mode power amplifier to generate the amplitude and phase modulated sinusoidal signals. The technique combines multiple clock phases with sinusoidally weighted circuits of the switching mode power amplifier to improve amplitude and phase modulated sinusoidal signal generation.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: August 7, 2018
    Assignee: Silicon Laboratories Inc.
    Inventors: Aaron J. Caffee, Brian G. Drost, Alessandro Piovaccari, Aslamali A. Rafi
  • Publication number: 20180190424
    Abstract: A technique for forming an integrated circuit including an inductor reduces magnetic coupling between the inductor and surrounding elements. The technique includes deliberate placement of circuit elements (e.g., terminals, pins, routing traces) in locations on the integrated circuit relative to a magnetic vector potential associated with the inductor and relative to a magnetic flux density field associated with the inductor to reduce or eliminate induced signals that degrade system performance.
    Type: Application
    Filed: January 4, 2017
    Publication date: July 5, 2018
    Inventors: Aaron J. Caffee, Brian G. Drost
  • Publication number: 20180191384
    Abstract: A technique that reduces or eliminates trading-off power amplifier efficiency and costly external filtering in amplitude and phase modulated sinusoidal signal generation uses multi-phase outphasing and a multi-phase switching mode power amplifier to generate the amplitude and phase modulated sinusoidal signals. The technique combines multiple clock phases with sinusoidally weighted circuits of the switching mode power amplifier to improve amplitude and phase modulated sinusoidal signal generation.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 5, 2018
    Inventors: Aaron J. Caffee, Brian G. Drost, Alessandro Piovaccari, Aslamali A. Rafi
  • Patent number: 10008981
    Abstract: An integrated clock generator includes a tunable LC oscillator, a tunable frequency synthesizer, and a processor. The tunable LC oscillator has an input for receiving an oscillator control signal, and an output for providing an oscillator clock signal. The tunable frequency synthesizer has a clock input coupled to the output of the tunable LC oscillator, a control input for receiving a synthesizer control signal, and an output for providing a clock output signal. The processor has an input for receiving a data input signal, a first output for providing the oscillator control signal, and a second output for providing the synthesizer control signal. The processor provides the oscillator control signal and the synthesizer control signal such that the tunable frequency synthesizer generates the output clock signal at a frequency indicated by the data input signal, and provides the synthesizer control signal further in response to a dynamic condition.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: June 26, 2018
    Assignee: Silicon Laboratories Inc.
    Inventors: Aaron J. Caffee, Brian G. Drost, Hendricus de Ruijter
  • Patent number: 9989927
    Abstract: A technique for sensing an environmental parameter is disclosed. The technique generates an oscillating signal using a variable resistance sensitive to a variable parameter. A frequency of the oscillating signal is directly dependent on the variable resistance. A time-to-digital converter generates a digital code indicative of the variable resistance. The digital code is generated based on the frequency of the oscillating signal and a second frequency of a reference clock signal. The second frequency is insensitive to the variable parameter. The variable resistance may be a metal resistor and the reference resistance may be generated using a capacitor that is switched at a particular frequency. The measured resistance may be used to control a voltage-controlled oscillator. The oscillating signal frequency may be converted to a digital signal and post-processed for use as an indicator of absolute temperature or other environmental parameter.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: June 5, 2018
    Assignee: Silicon Laboratories Inc.
    Inventor: Aaron J. Caffee
  • Publication number: 20180150031
    Abstract: A technique for sensing an environmental parameter is disclosed. The technique generates an oscillating signal using a variable resistance sensitive to a variable parameter. A frequency of the oscillating signal is directly dependent on the variable resistance. A time-to-digital converter generates a digital code indicative of the variable resistance. The digital code is generated based on the frequency of the oscillating signal and a second frequency of a reference clock signal. The second frequency is insensitive to the variable parameter. The variable resistance may be a metal resistor and the reference resistance may be generated using a capacitor that is switched at a particular frequency. The measured resistance may be used to control a voltage-controlled oscillator. The oscillating signal frequency may be converted to a digital signal and post-processed for use as an indicator of absolute temperature or other environmental parameter.
    Type: Application
    Filed: November 30, 2016
    Publication date: May 31, 2018
    Inventor: Aaron J. Caffee
  • Patent number: 9979404
    Abstract: A technique that reduces or eliminates trading-off power amplifier efficiency and costly external filtering in amplitude and phase modulated sinusoidal signal generation uses multi-phase outphasing and a multi-phase switching mode power amplifier to generate the amplitude and phase modulated sinusoidal signals. The technique combines multiple clock phases with sinusoidally weighted circuits of the switching mode power amplifier to improve amplitude and phase modulated sinusoidal signal generation.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: May 22, 2018
    Assignee: Silicon Laboratories Inc.
    Inventors: Brian G. Drost, Aaron J. Caffee, Alessandro Piovaccari, Aslamali A. Rafi
  • Patent number: 9813023
    Abstract: A low-complexity differential inductor and common-mode impedance network for reducing effects of flicker noise in an oscillator output signal have been disclosed. An oscillator includes a planar conductive loop comprising a first terminal, a second terminal, and a center tap. The planar conductive loop is formed from a first conductive layer above an integrated circuit substrate. The center tap is coupled to a first power supply node. The oscillator includes a planar conductive structure extending from a first point proximate to the center tap. The planar conductive structure extends along a line of symmetry of the planar conductive loop to a second point proximate to the first terminal and the second terminal. The planar conductive structure may be formed from the first conductive layer and may be directly coupled to the center tap.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: November 7, 2017
    Assignee: Silicon Laboratories Inc.
    Inventor: Aaron J. Caffee
  • Patent number: 9698807
    Abstract: A technique for on-chip time measurement includes dynamically scaling a range of a time-based digital-to-analog converter to enhance resolution of the time measurement. An apparatus includes a first time-based digital-to-analog converter configured to generate a first clock signal based on a first reference clock signal and a first digital code. The apparatus includes a second time-based digital-to-analog converter configured to generate a second clock signal based on a second reference clock signal and a second digital code. The first reference clock signal has a first frequency and the second reference clock signal has a second frequency that is harmonically related to the first frequency. The apparatus includes a time signal converter configured to generate an output signal having a level indicative of a time-of-arrival of a first edge of the first clock signal relative to a time-of-arrival of a second edge of the second clock signal.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: July 4, 2017
    Assignee: Silicon Laboratories Inc.
    Inventors: Aaron J. Caffee, Brian G. Drost, Volodymyr Kratyuk
  • Publication number: 20170179881
    Abstract: A low-complexity differential inductor and common-mode impedance network for reducing effects of flicker noise in an oscillator output signal have been disclosed. An oscillator includes a planar conductive loop comprising a first terminal, a second terminal, and a center tap. The planar conductive loop is formed from a first conductive layer above an integrated circuit substrate. The center tap is coupled to a first power supply node. The oscillator includes a planar conductive structure extending from a first point proximate to the center tap. The planar conductive structure extends along a line of symmetry of the planar conductive loop to a second point proximate to the first terminal and the second terminal. The planar conductive structure may be formed from the first conductive layer and may be directly coupled to the center tap.
    Type: Application
    Filed: December 16, 2015
    Publication date: June 22, 2017
    Inventor: Aaron J. Caffee