Patents by Inventor Aaron J. Nygren

Aaron J. Nygren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Command protocol for adjustment of write timing delay
    Patent number: 9798353
    Abstract: Apparatuses are provided for adjusting the write timing. For instance, the apparatus can include an address/control bus, a write clock data recovery (WCDR) signal bus, and a timing adjustment module. The address/control bus can be configured to concurrently enable a WCDR mode of operation and an active mode of operation. The WCDR signal bus can be configured to transmit WCDR data to a memory device during the WCDR mode of operation. And the timing adjustment module can be configured to adjust a timing based on a phase shift in the WCDR data.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: October 24, 2017
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Aaron J. Nygren, Ming-Ju E. Lee, Shadi M. Barakat, Xiaoling Xu, Toan D. Pham, W. Fritz Kruger, Michael J. Litt
  • Data bus inversion coding
    Patent number: 8909840
    Abstract: Techniques are disclosed relating to data inversion encoding. In one embodiment, an apparatus includes an interface circuit. The interface circuit is configured to perform first and second data bursts that include respective pluralities of data transmissions encoded using an inversion coding scheme. In such an embodiment, the initial data transmission of the second data burst is encoded using the final data transmission of the first data burst. In some embodiments, the first and second data bursts correspond to successive write operations or successive read operations to a memory module from a memory PHY.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: December 9, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Aaron J. Nygren, Anwar Kashem, Bryan Black, James Michael O'Connor, Warren Fritz Kruger
  • COMMAND PROTOCOL FOR ADJUSTMENT OF WRITE TIMING DELAY
    Publication number: 20130290767
    Abstract: Apparatuses are provided for adjusting the write timing. For instance, the apparatus can include an address/control bus, a write clock data recovery (WCDR) signal bus, and a timing adjustment module. The address/control bus can be configured to concurrently enable a WCDR mode of operation and an active mode of operation. The WCDR signal bus can be configured to transmit WCDR data to a memory device during the WCDR mode of operation. And the timing adjustment module can be configured to adjust a timing based on a phase shift in the WCDR data.
    Type: Application
    Filed: June 18, 2013
    Publication date: October 31, 2013
    Inventors: Aaron J. NYGREN, Ming-Ju E. Lee, Shadi M. Barakat, Xiaoling Xu, Toan D. Pham, W. Fritz Kruger, Michael J. Litt
  • DATA BUS INVERSION CODING
    Publication number: 20130159584
    Abstract: Techniques are disclosed relating to data inversion encoding. In one embodiment, an apparatus includes an interface circuit. The interface circuit is configured to perform first and second data bursts that include respective pluralities of data transmissions encoded using an inversion coding scheme. In such an embodiment, the initial data transmission of the second data burst is encoded using the final data transmission of the first data burst. In some embodiments, the first and second data bursts correspond to successive write operations or successive read operations to a memory module from a memory PHY.
    Type: Application
    Filed: December 19, 2011
    Publication date: June 20, 2013
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Aaron J. Nygren, Anwar Kashem, Bryan Black, James Michael O'Connor, Warren Fritz Kruger