Abstract: Systems and techniques for pin cutouts in memory modules (e.g., Dual In-line Memory Modules (DIMMs)) are described. A memory module includes one or more memory integrated circuits mounted on a printed circuit board. The memory module also includes at least one additional component, including, for example, a power manager integrated circuit, buffers, and inductors. The memory module also includes one or more rows of pins to provide an electrical connection to a motherboard. One or more rows include a pin cutout wherein some pins are removed or not placed in the row. The pin cutout allows a component to be mounted on the PCB in the foregone board area.

Abstract: A buffer device for combining and splitting data strobes (DQS) for pseudo channels in memory systems is described. In one or more implementations, a buffer device includes strobe logic configured to combine multiple data strobes for separate pseudo channels into a combined data strobe for transmission to memory chips connected to the buffer device, and split multiple combined data strobes received from the memory chips into separate data strobes per pseudo channel for transmission to a system on chip. The buffer device is positioned between the memory chips and the system on chip to manage data strobe signals bidirectionally while maintaining pseudo channel independence on the system side and shared strobe functionality on the memory side.

Abstract: An extended length memory module with multiple channels is described. In one or more implementations, a memory module comprises a printed circuit board having a first length that is greater than a second length of memory modules. The memory module includes multiple memory chips mounted on the printed circuit board. Multiple buffers are also mounted on the printed circuit board, and those buffers are configured to handle memory operations across at least three channels for accessing the memory chips. The greater length of the printed circuit board allows for increased memory capacity and bandwidth within a single module form factor while maintaining compatibility with existing memory architectures.

Abstract: A multi-die memory package with individually accessible command/address (CA) pins is described. In one or more implementations, a memory chip includes a plurality of memory dies arranged in a stacked configuration, a package substrate, and a plurality of command/address pins. Each command/address pin of the plurality of command/address pins is individually accessible via one or more corresponding interconnects to the package substrate or an intermediate component. The intermediate component may be configured to control use of the command/address pins and data pins at the memory chip level.

Abstract: A buffer for error correction in memory modules is described. In one or more implementations, a memory module (e.g., a DIMM) configured for error correction code (ECC) includes a plurality of memory chips, wherein at least one memory chip includes memory die split between a first memory subchannel and a second memory subchannel. The memory module also includes a plurality of registered clock drivers (RCDs), wherein at least one RCD is configured to handle input addresses for both the first memory subchannel and the second memory subchannel. This configuration allows for efficient use of memory resources and flexibility in memory addressing, particularly for scenarios requiring ECC functionality or when dealing with memory chips of different capacities.

Abstract: Systems and techniques for vertical module connectors with pin-clamp mechanisms are described. An example module connector includes two cross-members, with each cross-member including at least one row of pins. Upon insertion, the pins are arranged to make electrical contact with pins on a memory module (e.g., a dual in-line memory module (DIMM)). The module connector also includes a clamping mechanism (e.g., a hinge assembly) that closes a first cross-member against or towards a second cross-member in response to or after insertion of the memory module. The module connector further includes a locking mechanism to maintain a closed state of the two cross-members and provide electrical contact between the row of pins on each cross-member and pins on the memory module. The described module connector allows for the insertion of memory modules with increased pins without reduced insertion force.

Abstract: A multi-die memory chip with individually accessible data (DQ) pins is described. In one or more implementations, a memory chip includes a plurality of memory die arranged in a stacked configuration, a package substrate, and a plurality of data pins that are individually accessible via corresponding connectors. The memory die may be separated into at least two ranks, with a first subset of the data pins associated with a first rank and a second subset of the data pins associated with a second rank. The individual accessibility of the first and second subsets of data pins enables the memory chip to operate in a multiplexed mode or an error correcting code mode.

Abstract: Implementations herein describe a system including a system-on-chip including at least a host and a dynamic random-access memory (DRAM) in communication with the SoC, the DRAM including at least an error correction code engine, the system configured to allow the host to write first data to the DRAM, calculate parity bits for the first write data, store the first write data and the parity bits in a DRAM core of the DRAM, allow the host to write second data to the DRAM, store the second write data in the DRAM core without calculating parity bits for the second write data, enable the DRAM to calculate parity bits of the second write data and compare the parity bits of the second write data to the parity bits of the first write data, and calculate a syndrome based on a comparison to correct errors detected in the DRAM core.

Abstract: A computer system includes device circuitry includes connectors, memory modules, and a retention mechanism. The memory modules are disposed within the connectors. The retention mechanism is connected to the memory modules. The retention mechanism includes slots. Each of the slots receives one of the memory modules.

Abstract: An electronic device includes a host device comprising memory controller circuitry and a memory IC device connected to the memory controller circuitry. The memory IC device includes memory devices and pins connected to the memory devices and the memory controller circuitry. The pins route signals to and from the memory devices. The pins are configurable based on configuration data to perform memory operations.

Abstract: Implementations herein describe a system including a system-on-chip including at least a host and a dynamic random-access memory (DRAM) in communication with the SoC, the DRAM including at least an error correction code engine, the system configured to allow the host to write first data to the DRAM, calculate parity bits for the first write data, store the first write data and the parity bits in a DRAM core of the DRAM, allow the host to write second data to the DRAM, store the second write data in the DRAM core without calculating parity bits for the second write data, enable the DRAM to calculate parity bits of the second write data and compare the parity bits of the second write data to the parity bits of the first write data, and calculate a syndrome based on a comparison to correct errors detected in the DRAM core.

Abstract: Implementations herein describe a system including a system-on-chip including at least a host and a dynamic random-access memory (DRAM) in communication with the SoC, the DRAM including at least an error correction code engine, the system configured to allow the host to write first data to the DRAM, calculate parity bits for the first write data, store the first write data and the parity bits in a DRAM core of the DRAM, allow the host to write second data to the DRAM, store the second write data in the DRAM core without calculating parity bits for the second write data, enable the DRAM to calculate parity bits of the second write data and compare the parity bits of the second write data to the parity bits of the first write data, and calculate a syndrome based on a comparison to correct errors detected in the DRAM core.

Abstract: Implementations herein describe a system including a system-on-chip and a dynamic random-access memory (DRAM) in communication with the SoC, the DRAM including at least a per row activation counting (PRAC) counter, the system configured to detect an error in the PRAC counter, transmit a signal to an alert signal logic block in the DRAM once the error in the PRAC counter has been detected, and allow the alert signal logic block to provide the signal to the SoC once the alert signal logic block receives the signal.

Abstract: A data processing system includes a memory responsive to receiving a read command to generate a hybrid read clock signal based on a setting of at least one mode register, and a data processor configured to program the at least one mode register including setting a read clock mode of the hybrid read clock signal to one of a plurality of settings. The plurality of settings includes an always on mode in which the hybrid read clock signal toggles continuously, and a read-only mode in which the hybrid read clock signal starts toggling in response to receiving the read command by the memory, and that continues to toggle at least to an end of a read postamble period following the read command. The data processor is also configured to receive data during a read cycle using the hybrid read clock signal.

Abstract: A high-bandwidth dual-inline memory module (HB-DIMM) includes a plurality of memory chips, a plurality of data buffer chips, and a register clock driver (RCD) circuit. The data buffer chips are coupled to respective sets of the memory chips and transmit data from the memory chips over a host bus at a data rate twice that of the memory chips. The RCD circuit includes a host bus interface and a memory interface coupled to the plurality of memory chips. The RCD circuit implements commands received over the host bus by routing command/address (C/A) signals to the memory chips for providing at least two independently addressable pseudo-channels, the RCD circuit addressing each respective pseudo-channel based on a chip identifier (CID) bit derived from the C/A signals.

Abstract: A data processor comprises data processor comprising a memory controller, wherein the data processor is configured to control the memory controller to program at least one mode register of a memory to set a read clock mode to one of a plurality of settings, wherein the plurality of settings includes a read-only mode in which the memory starts a read clock signal in response to a command, and subsequently perform a read cycle by receiving data during the read cycle using the read clock signal.

Abstract: A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The mode register provides the read clock mode signal in response to a read clock mode, wherein the read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously when the read clock mode is a first mode, and as a strobe signal that is active only in response to the memory receiving a read command when the read clock mode is a second mode.

Abstract: A memory device selects a burst length to complete memory transactions. The memory device receives a first memory transaction and a second memory transaction. The memory device completes the first memory transaction using the first burst length. First data and metadata associated with the first memory transaction are transmitted to complete the first memory transaction. The memory device further completes the second memory transaction using a second burst length. A number of bursts in the first burst length is greater than a number of burst the second burst length.

Abstract: A memory includes a read clock state machine and a read clock driver circuit. The read clock state machine has a first input for receiving a read command signal, a second input for receiving a read clock mode signal, and an output for providing a drive enable signal. The read clock driver circuit has an output for providing a read clock signal in response to a clock signal when the drive enable signal is active. When the read clock mode signal indicates a read-only mode, the read clock state machine starts toggling the read clock signal during a read preamble period before a data transmission of a first read command, and continues toggling the read clock signal for at least a read postamble period following the data transmission of the first read command.

Abstract: A system and technique for buffering data locally within a memory device to allow access to data associated with multiple different rows within the memory device. The memory device includes memory bank circuitry having memory cells and sense amplifier circuitry coupled to the memory bank circuitry. The memory device further includes buffer circuitry coupled to an output of the sense amplifier circuitry. Further, the memory device includes selection circuitry. The selection circuitry receives a first data signal from the sense amplifier circuitry and a second data signal from the buffer circuitry, and outputs a selected one of the first data signal and the second data signal.