Abstract: An apparatus, system, and method for improved memory control are provided. A circuit can include controller circuitry configured to determine, based on a speed of silicon of a memory, a read strobe code that adjusts a data clock to account for a difference between a reference clock and a data clock in terms of a number of unit intervals (UIs) and a read strobe code, a receive delay locked loop to receive the difference and delay the data clock by the number of UI and read strobe codes resulting in a delayed data clock, and a sampling amplifier to sample data from the memory based on the delayed data clock.

Abstract: An apparatus for providing homestyle egg product portions on a commercial scale is described. The apparatus includes a plurality of moving heated pockets, and a plurality of mixers. Each heated pocket is capable of holding an egg product portion, and each mixer is capable of stirring an egg product portion held in a heated pocket to yield a stirred egg product portion. The apparatus can further include a plurality of groupers. Each grouper is capable of gathering stirred egg product portions held in a moving heated pocket. Methods for producing homestyle egg product portions on a commercial scale are also described.

Abstract: A microwavable, refrigerated scrambled egg composition. The composition includes a first component that is frozen precooked egg portions. At least about 50% by weight of the frozen egg portions are pieces that are at least about ½ inch in one dimension. The second component is a slurry including pasteurized liquid egg and pregelatinized modified food starch. The precooked egg portions are from about 50% to about 85% by weight of the total scrambled egg composition and the slurry is from about 15% to about 50% by weight of the total scrambled egg composition. Processes for making and methods of using the microwavable, refrigerated scrambled egg composition are also provided.

Abstract: An apparatus for providing homestyle egg product portions on a commercial scale is described. The apparatus includes a plurality of moving heated pockets, and a plurality of mixers. Each heated pocket is capable of holding an egg product portion, and each mixer is capable of stirring an egg product portion held in a heated pocket to yield a stirred egg product portion. The apparatus can further include a plurality of groupers. Each grouper is capable of gathering stirred egg product portions held in a moving heated pocket. Methods for producing homestyle egg product portions on a commercial scale are also described.

Abstract: A microwavable, refrigerated scrambled egg composition. The composition comprises a first component that is frozen precooked egg portions. At least about 50% by weight of the frozen egg portions are pieces that are at least about ½ inch in one dimension. The second component is a slurry comprising pasteurized liquid egg and pregelatinized modified food starch. The precooked egg portions are from about 50% to about 85% by weight of the total scrambled egg composition and the slurry is from about 15% to about 50% by weight of the total scrambled egg composition. Processes for making and methods of using the microwavable, refrigerated scrambled egg composition are also provided.

Abstract: De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits.

Abstract: In one embodiment, a receiver includes a voltage margin controller, a set of first components coupled to the voltage margin control, and a set of offset compensation controllers coupled to the set of first components.

Abstract: An integrated circuit includes clock deskew circuitry. The deskew circuitry includes a loop circuit to align an input clock signal with an output clock signal, and also aligns transmitted data with the output clock signal.

Abstract: A system and method for encoding and receiving data is provided. The data is encoded as a pulse amplitude modulated signal such that the amplitude signals do not transition from the highest signal level to the lowest signal level and do not transition from the lowest signal level to the highest signal level. The encoding and decoding is performed in some embodiments via a lookup table, and in further embodiments is designed to minimize the step between sequential pulse amplitude modulated symbols.

Abstract: A circuit to synchronize the phase of a distributed clock signal to a received clock signal. Embodiments include a control loop comprising a phase interpolator, a clock distribution network, and a data receiver. The clock distribution network provides a sampling clock signal to clock the data receiver. The data receiver receives as its input the received clock signal. Control logic maps a subset of the output samples to a value, and this value is added to the phase introduced by the phase interpolator to provide an updated phase. Embodiments include a second phase interpolator and a second distribution network to clock a second data receiver, where the second data receiver receives the data. The control logic adjusts the second phase interpolator in the same way that it adjusts the phase interpolator. The two data receivers are matched to each other, and the two clock distribution networks are matched to each other. Other embodiments are described and claimed.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a clocking architecture using a bidirectional clock. In an embodiment, a chip includes a bidirectional clock port capable of being statically configured to receive or to transmit a reference clock. In one embodiment, the chip includes a first port to receive data and a second port, wherein the chip repeats at least a portion of the data that it receives on the first port to a transmitter at the second port. Other embodiments are described and claimed.

Abstract: A method, circuit, and system are disclosed. In one embodiment, the method comprises receiving a differential clock signal from two clock signal lines into a first differential pair of transistors of a first size, receiving the differential clock signal from the two clock signal lines into a second differential pair of transistors of a size smaller than the first size, converting the differential clock signal into a single-ended clock signal, outputting the single-ended clock signal through an inverter, and synchronizing any differential clock phase error by controlling the transconductance between the first differential pair of transistors and the second differential pair of transistors.

Abstract: A global clock recovery circuit and port circuit determine and combine static phase adjustment information and dynamic phase adjustment information for multiple data signals. Static phase adjustment information is determined for each of the multiple data signals, and dynamic phase adjustment information is determined in common for the multiple data signals.

Abstract: An integrated circuit includes clock deskew circuitry. The deskew circuitry includes multiple loop circuits to align a received clock with a data eye, and to reduce the effects of clock drift caused by voltage and temperature variations. The loop circuits include phase interpolators to produce local clock signals. Local clock signals are provided to seqiuential elements through local clock trees and are also provided to a phase detector through a dummy local clock tree. The operation of the phase interpolators is influenced by the phase detector.

Abstract: De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits.

Abstract: A data driver drives a data signal on a channel, and a current mode driver drives a varying current on the channel to reduce crosstalk.

Abstract: A system and method for encoding and receiving data is provided. The data is encoded as a pulse amplitude modulated signal such that the amplitude signals do not transition from the highest signal level to the lowest signal level and do not transition from the lowest signal level to the highest signal level. The encoding and decoding is performed in some embodiments via a lookup table, and in further embodiments is designed to minimize the step between sequential pulse amplitude modulated symbols.

Abstract: De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits.

Abstract: A system and method for encoding and receiving data is provided. The data is encoded as a pulse amplitude modulated signal such that the amplitude signals do not transition from the highest signal level to the lowest signal level and do not transition from the lowest signal level to the highest signal level. The encoding and decoding is performed in some embodiments via a lookup table, and in further embodiments is designed to minimize the step between sequential pulse amplitude modulated symbols.

Abstract: Clock error detections circuits can detect clock duty cycle error and/or quadrature phase error. During an evaluation phase, capacitors are charged. During an evaluation phase, the capacitors are unequally discharged based on the error. A positive feedback mechanism latches the result.