Abstract: Systems and methods disclosed herein allow for efficiently managing unmapped blocks to extend life of solid-state drives. In one aspect, a method includes: measuring a level of over-provisioning (“OP”) in a storage device and operating it in a first mode of operation while the OP satisfies a first threshold. The method also includes: changing to a second mode of operation if the OP does not satisfy the first threshold. While operating in the second mode of operation, the method includes: (i) determining an unmapped portion of a declared storage capacity of the storage device; and (ii) determining whether processing a write command would reduce the unmapped portion to less than a second threshold. If processing the write command wouldn't reduce the unmapped portion to less than the second threshold, the method includes: accepting and processing the write command. Else, the method includes: forgoing acceptance and processing of the write command.

Abstract: Systems and methods disclosed herein allow for efficiently managing unmapped blocks to extend life of solid-state drives. In one aspect, a method includes: determining a quantity of unmapped storage units in the storage device and operating the storage device in a first mode of operation while the quantity satisfies a first threshold. The method also includes: changing to a second mode of operation if the quantity of unmapped storage units doesn't satisfy the first threshold. While operating in the second mode of operation, the method includes: determining whether processing a write command would reduce the quantity of unmapped storage units to a quantity less than a second threshold. If processing the write command wouldn't reduce the quantity of unmapped storage units to a quantity less than the second threshold, the method includes: accepting and processing the write command. Else, the method includes: forgoing acceptance and processing of the write command.

Abstract: A memory controller configures a plurality of word lines associated with a respective block of a 3D memory device in a first configuration, where the first configuration includes a set of configuration parameters for each word line of the plurality of word lines determined at least in part on the vertical positions of each word line relative to a substrate of the 3D memory device and, while the plurality of word lines are configured in the first configuration, writes data to and reads data from the respective block. For the respective block, the memory controller: adjusts a first parameter in the respective set of configuration parameters corresponding to a respective word line of the plurality of word lines in response to detecting a first trigger condition as to the respective word line and, after adjusting the first parameter, writes data to and reads data from the respective word line.

Abstract: The various implementations described herein include systems, methods and/or devices for modifying an error correction format of a respective memory portion of non-volatile memory in a storage device. In one aspect, the method includes, for respective memory portions of the non-volatile memory, obtaining a performance metric of the respective memory portion, and modifying a current error correction format in accordance with the measured performance metric, the current error correction format corresponding to a code rate, codeword structure, and error correction type. Furthermore, data is stored, and errors are detected and corrected, in the respective memory portion in accordance with the modified error correction format. The current and modified error correction formats are distinct, and comprise two of a sequence of predefined error correction formats, wherein a plurality of the sequence of predefined error correction formats have a same number of error correction bits and different numbers of data bits.

Abstract: Systems, methods and/or devices are used to enable tracking intermix of writes and un-map commands across power cycles. In one aspect, the method includes (1) receiving, at a storage device, a plurality of commands from a host, the storage device including non-volatile memory, (2) maintaining a log corresponding to write commands and un-map commands from the host, (3) maintaining a mapping table in volatile memory, the mapping table used to translate logical addresses to physical addresses, (4) saving the mapping table, on a scheduled basis that is independent of the un-map commands, to the non-volatile memory of the storage device, (5) saving the log to the non-volatile memory, and (6) upon power up of the storage device, rebuilding the mapping table from the saved mapping table in the non-volatile memory of the storage device and from the saved log in the non-volatile memory of the storage device.

Abstract: Systems and methods disclosed herein allow for efficiently managing unmapped blocks to extend life of solid-state drives. In one aspect, a method includes: measuring a level of over-provisioning (“OP”) in a storage device and operating it in a first mode of operation while the OP satisfies a first threshold. The method also includes: changing to a second mode of operation if the OP does not satisfy the first threshold. While operating in the second mode of operation, the method includes: (i) determining an unmapped portion of a declared storage capacity of the storage device; and (ii) determining whether processing a write command would reduce the unmapped portion to less than a second threshold. If processing the write command wouldn't reduce the unmapped portion to less than the second threshold, the method includes: accepting and processing the write command. Else, the method includes: forgoing acceptance and processing of the write command.

Abstract: Systems and methods disclosed herein allow for efficiently managing unmapped blocks to extend life of solid-state drives. In one aspect, a method includes: determining a quantity of unmapped storage units in the storage device and operating the storage device in a first mode of operation while the quantity satisfies a first threshold. The method also includes: changing to a second mode of operation if the quantity of unmapped storage units doesn't satisfy the first threshold. While operating in the second mode of operation, the method includes: determining whether processing a write command would reduce the quantity of unmapped storage units to a quantity less than a second threshold. If processing the write command wouldn't reduce the quantity of unmapped storage units to a quantity less than the second threshold, the method includes: accepting and processing the write command. Else, the method includes: forgoing acceptance and processing of the write command.

Abstract: A memory controller receives a command to perform a memory operation, the command including a data packet comprising a plurality of data divisions. In response to receiving the command, for each individual memory device, the memory controller assigns to the individual memory device a respective data division, the respective data division including a plurality of data segments, and determines a single relative memory address associated with an address specified by the received command. The memory controller assembles a sub-request comprising a single contiguous instruction portion, which includes the single relative memory address and one or more instructions to perform the memory operation, and the respective data division, the respective data division following the single contiguous instruction portion, and transmits the sub-request to every memory portion of the number of memory portions of the individual memory device.

Abstract: A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously.

Abstract: The various implementations described herein include systems, methods and/or devices method for reading data stored in a non-volatile storage device having a plurality of physical memory portions having a predefined sequence of physical locations in one or more non-volatile memory devices. In one aspect, the method includes, executing a command for reading a requested logical group of data having a specified logical address, including mapping the logical address to physical locations in the storage device. If the physical locations correspond to two physical memory portions at sequential physical locations, a single sequential read operation is used to read data from the two physical memory portions. If the physical locations correspond to two physical memory portions at non-sequential physical locations, two read operations are used to read data from the two non-sequential physical memory portions.

Abstract: The various implementations described herein include systems, methods and/or devices for encoding and decoding data for memory portions of non-volatile memory in a storage device. In one aspect, the method includes, for respective memory portions of the non-volatile memory, in accordance with an error correction format of the respective memory portion: encoding data to produce codewords; storing the codewords in the respective memory portion; and decoding the codewords to produce decoded data. Furthermore, each memory portion of the non-volatile memory has a corresponding error correction format corresponding to a code rate, a codeword structure, and an error correction type, and comprising one of a sequence of predefined error correction formats. A plurality of the predefined error correction formats have a same number of error correction bits and different numbers of data bits, where at least two memory portions have distinct error correction formats.

Abstract: A memory controller receives a command to perform a memory operation, the command including a data packet comprising a plurality of data divisions. In response to receiving the command, for each individual memory device, the memory controller assigns to the individual memory device a respective data division, the respective data division including a plurality of data segments, and determines a single relative memory address associated with an address specified by the received command. The memory controller assembles a sub-request comprising a single contiguous instruction portion, which includes the single relative memory address and one or more instructions to perform the memory operation, and the respective data division, the respective data division following the single contiguous instruction portion, and transmits the sub-request to every memory portion of the number of memory portions of the individual memory device.

Abstract: The various implementations described herein include systems, methods and/or devices for modifying an error correction format of a respective memory portion of non-volatile memory in a storage device. In one aspect, the method includes, for respective memory portions of the non-volatile memory, obtaining a performance metric of the respective memory portion, and modifying a current error correction format in accordance with the measured performance metric, the current error correction format corresponding to a code rate, codeword structure, and error correction type. Furthermore, data is stored, and errors are detected and corrected, in the respective memory portion in accordance with the modified error correction format. The current and modified error correction formats are distinct, and comprise two of a sequence of predefined error correction formats, wherein a plurality of the sequence of predefined error correction formats have a same number of error correction bits and different numbers of data bits.

Abstract: A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously.

Abstract: A single command initiates a first read operation and sequence of one or more additional read operations from the same portion of memory. The one or more additional read operations are terminable after the first read operation provides a first plurality of data values that is made available to a requesting device and/or module. In some implementations, the first plurality of data values includes hard information values. Subsequent pluralities of data values are generated from the same portion of memory until a terminating event occurs. In some implementations, until a terminating event occurs, a respective hybrid plurality of data values is generated by combining the latest read plurality of data values with one of a previously generated hybrid plurality of data values and the first plurality of data values. Each hybrid plurality of data values is representative of a corresponding plurality of soft information values.

Abstract: Systems, methods and/or devices are used to enable tracking intermix of writes and un-map commands across power cycles. In one aspect, the method includes (1) receiving, at a storage device, a plurality of commands from a host, the storage device including non-volatile memory, (2) maintaining a log corresponding to write commands and un-map commands from the host, (3) maintaining a mapping table in volatile memory, the mapping table used to translate logical addresses to physical addresses, (4) saving the mapping table, on a scheduled basis that is independent of the un-map commands, to the non-volatile memory of the storage device, (5) saving the log to the non-volatile memory, and (6) upon power up of the storage device, rebuilding the mapping table from the saved mapping table in the non-volatile memory of the storage device and from the saved log in the non-volatile memory of the storage device.

Abstract: A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously.

Abstract: A storage controller has multiple processors, divided into groups, each of which handles a different stage of a pipelined process of performing host reads and writes. In some embodiments, the storage controller operates with a flash memory module, and includes a first processor group, a second processor group and a third processor group, each having one or more processors for handling a different stage of a pipelined execution of host storage commands. With respect to a first host command, a first processor of the first processor group, a first processor of the second processor group, and a first processor of the third processor group comprise a first pipeline, and with respect to a second host command, a second processor of the first processor group, a second processor of the second processor group, and a second processor of the third processor group comprise a second pipeline.

Abstract: A memory controller configures a plurality of word lines associated with a respective block of a 3D memory device in a first configuration, where the first configuration includes a set of configuration parameters for each word line of the plurality of word lines determined at least in part on the vertical positions of each word line relative to a substrate of the 3D memory device and, while the plurality of word lines are configured in the first configuration, writes data to and reads data from the respective block. For the respective block, the memory controller: adjusts a first parameter in the respective set of configuration parameters corresponding to a respective word line of the plurality of word lines in response to detecting a first trigger condition as to the respective word line and, after adjusting the first parameter, writes data to and reads data from the respective word line.

Abstract: A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously.