Abstract: A method includes, in a data storage device that includes a non-volatile memory and a controller coupled to a non-volatile memory, the controller including a bus and a processor coupled to the bus, accessing a volatile memory included in the controller via a first interface. The volatile memory is coupled to the bus via the first interface. The data storage device further includes a resistive random access memory (ReRAM) having a second interface. The method also includes storing data at the ReRAM via the second interface. The ReRAM is coupled to the bus via the second interface. The controller is configured to store user data at the non-volatile memory via a dedicated controller-to-non-volatile memory interface.

Abstract: A method includes, in a data storage device that includes a non-volatile memory and a resistive random access memory (ReRAM) on the same die, receiving data from a memory controller via a bus. The method also includes routing the data to data latches of the non-volatile memory via a first path and to the ReRAM via a second path distinct from the first path.

Abstract: A method and system for intelligent bit recovery identifies toggling bits, which change in value from one read to the next, and examines a subset of potential bit patterns. The subset is a fraction of the potential bit patterns, and is based on an understanding of the flash memory and the problems that may cause the toggling bits. The intelligent bit recovery may analyze at least one aspect of the flash memory to identify a problem, or plurality of problems, that is potentially causing the toggling bits, and to select the subset of potential bit patterns as potential solutions. The subset of potential bit patterns examined by the intelligent bit recovery is a small fraction of the entire set of potential bit patterns.

Abstract: Methods and systems are disclosed herein for detecting problems related to copyback programming. After the copyback data is read into the internal flash buffer, a part of the copyback data stored in the internal flash buffer (such as spare data) is analyzed to determine whether there are any errors in a part of the copyback data read. The analysis may be used by the flash memory in one or more ways related to the current copyback operation, subsequent copyback operations, subsequent treatment of the data in the current copyback operation, and subsequent treatment of the section in memory associated with the source page.

Abstract: A mechanism is presented memory circuits, such a NAND-type flash memories, to autonomously protect themselves from temporary and short power drops. A detection mechanism looks for the supply voltage to drop below a function voltage for a period of time. When such an event occurs, a suspend mechanism is activated, and after completing the last micro-operation (such as a program pulse) the memory freezes. When power is again stable at an operational level, the suspended operation is resumed. The memory controller can then be notified upon occurrence of such voltage drop by polling a special status bit. Examples of how the pausing can be implemented include altering of clock signals and suspending sub-phases of larger operations.

Abstract: A mechanism is presented memory circuits, such a NAND-type flash memories, to autonomously protect themselves from temporary and short power drops. A detection mechanism looks for the supply voltage to drop below a function voltage for a period of time. When such an event occurs, a suspend mechanism is activated, and after completing the last micro-operation (such as a program pulse) the memory freezes. When power is again stable at an operational level, the suspended operation is resumed. The memory controller can then be notified upon occurrence of such voltage drop by polling a special status bit. Examples of how the pausing can be implemented include altering of clock signals and suspending sub-phases of larger operations.

Abstract: Methods and systems are disclosed herein for detecting problems related to copyback programming. After the copyback data is read into the internal flash buffer, a part of the copyback data stored in the internal flash buffer (such as spare data) is analyzed to determine whether there are any errors in a part of the copyback data read. The analysis may be used by the flash memory in one or more ways related to the current copyback operation, subsequent copyback operations, subsequent treatment of the data in the current copyback operation, and subsequent treatment of the section in memory associated with the source page.

Abstract: A method and system intelligent bit recovery is provided. The intelligent bit recovery determines which bits are toggling, and examines a subset of the potential bit patterns to determine which in the subset of potential bit patterns is valid. The subset is a fraction of the potential bit patterns, and is based on an understanding of the flash memory and the problems that may cause the toggling bits. The intelligent bit recovery may analyze at least one aspect of the flash memory to identify which problem is potentially causing the toggling bits, and to select the subset of potential bit patterns as solutions for the determined problem. Or, the intelligent bit recovery selects potential bit patterns for multiple potential problems. In either way, the subset of potential bit patterns examined by the intelligent bit recovery is a small fraction of the entire set of potential bit patterns.

Abstract: Disclosed is a system, method, and program for mapping logical addresses to physical sectors on a storage device including at least one storage medium surface. A determination is made of logical addresses that are specified to be stored in a high throughput region on one storage medium surface. At least two read/write heads operate on the storage medium surface including the high throughput region to increase performance of access operations in the high throughput region. A mapping is generated of the determined logical addresses to the high throughput region. The logical addresses mapped to the high throughput region are capable of being non-contiguous.