Abstract: A multi-level DAC includes first and second level resistor ladders, and a dual-switch ladder interconnect reduces DNL at tap-point transitions between first-level ladder resistors. For each first level resistor N, the switch-interconnect network includes dual (first/second) switches connectable to a resistor-top node NT, and dual (third/fourth) switches selectively connectable to a resistor-bottom node NB. The first switch is operable to connect NT to a top tap switch operable to select NT as a top tap point, and the fourth interconnect switch is operable to connect NB to a bottom tap switch operable to select NB as a bottom tap point. The first and fourth switches are connected, forming an outer loop that includes top and bottom tap points. The second switch connects to a top second-level resistor RT, and the third switch connects to a bottom second-level resistor RB, forming an inner loop that includes the series-connected second-level resistors.

Abstract: A phase look loop (PLL) device has a dynamic lock range that is based on a temperature measured during a calibration process. The PLL device includes a calibration circuit configured to receive a temperature reading corresponding to a junction temperature of the PLL device during the calibration process. Based on this temperature reading, the calibration circuit initiates a preset procedure that presets a control voltage of a voltage control oscillator in the PLL device. The preset procedure implements a calibration function defined by a slope with a numerator component and a denominator component. The numerator component corresponds to a range of the control voltage, whereas the denominator component corresponds to a range of ambient temperatures within which the PLL device operates.

Abstract: A multi-level DAC includes first and second level resistor ladders, and a dual-switch ladder interconnect reduces DNL at tap-point transitions between first-level ladder resistors. For each first level resistor N, the switch-interconnect network includes dual (first/second) switches connectable to a resistor-top node NT, and dual (third/fourth) switches selectively connectable to a resistor-bottom node NB. The first switch is operable to connect NT to a top tap switch operable to select NT as a top tap point, and the fourth interconnect switch is operable to connect NB to a bottom tap switch operable to select NB as a bottom tap point. The first and fourth switches are connected, forming an outer loop that includes top and bottom tap points. The second switch connects to a top second-level resistor RT, and the third switch connects to a bottom second-level resistor RB, forming an inner loop that includes the series-connected second-level resistors.

Abstract: A phase look loop (PLL) device has a dynamic lock range that is based on a temperature measured during a calibration process. The PLL device includes a calibration circuit configured to receive a temperature reading corresponding to a junction temperature of the PLL device during the calibration process. Based on this temperature reading, the calibration circuit initiates a preset procedure that presets a control voltage of a voltage control oscillator in the PLL device. The preset procedure implements a calibration function defined by a slope with a numerator component and a denominator component. The numerator component corresponds to a range of the control voltage, whereas the denominator component corresponds to a range of ambient temperatures within which the PLL device operates.

Abstract: A phase look loop (PLL) device has a dynamic lock range that is based on a temperature measured during a calibration process. The PLL device includes a calibration circuit configured to receive a temperature reading corresponding to a junction temperature of the PLL device during the calibration process. Based on this temperature reading, the calibration circuit initiates a preset procedure that presets a control voltage of a voltage control oscillator in the PLL device. The preset procedure implements a calibration function defined by a slope with a numerator component and a denominator component. The numerator component corresponds to a range of the control voltage, whereas the denominator component corresponds to a range of ambient temperatures within which the PLL device operates.

Abstract: A multi-level DAC includes first and second level resistor ladders, and a dual-switch ladder interconnect reduces DNL at tap-point transitions between first-level ladder resistors. For each first level resistor N, the switch-interconnect network includes dual (first/second) switches connectable to a resistor-top node NT, and dual (third/fourth) switches selectively connectable to a resistor-bottom node NB. The first switch is operable to connect NT to a top tap switch operable to select NT as a top tap point, and the fourth interconnect switch is operable to connect NB to a bottom tap switch operable to select NB as a bottom tap point. The first and fourth switches are connected, forming an outer loop that includes top and bottom tap points. The second switch connects to a top second-level resistor RT, and the third switch connects to a bottom second-level resistor RB, forming an inner loop that includes the series-connected second-level resistors.

Abstract: A phase look loop (PLL) device has a dynamic lock range that is based on a temperature measured during a calibration process. The PLL device includes a calibration circuit configured to receive a temperature reading corresponding to a junction temperature of the PLL device during the calibration process. Based on this temperature reading, the calibration circuit initiates a preset procedure that presets a control voltage of a voltage control oscillator in the PLL device. The preset procedure implements a calibration function defined by a slope with a numerator component and a denominator component. The numerator component corresponds to a range of the control voltage, whereas the denominator component corresponds to a range of ambient temperatures within which the PLL device operates.

Abstract: The present invention provides an electrolytic cell for use in a process for real time monitoring of a chemical bath used in the fabrication of a semiconductor wafer and having different metal ions therein. In one embodiment, the electrolytic cell comprises a fluid chamber having an inlet, an outlet and chamber walls, and channel electrodes coupled to the chamber walls. The inlet and outlet permit a throughflow of at least of a portion of the chemical bath. Each of the channel electrodes corresponds to one of the different metal ions. Each channel electrode is energized to a detection potential selected to provide electrical conduction when the corresponding different metal ion reaches a prescribed concentration.

Abstract: Multilayer circuit devices include a plurality of metallized patterns thereon, said patterns being separated by a polymeric dielectric film. The various metallized patterns are interconnected by means of microvias through the polymeric film or films. Each of the metallizations is a composite including in succession from the substrate or from the polymeric film, a layer of titanium (Ti), a layer of titanium and palladium alloy (Ti/Pd), a layer of copper (Cu), and a layer of titanium and palladium alloy (Ti/Pd). The Ti-Ti/Pd-Cu-Ti/Pd composite is hereinafter referred to as TCT. The adhesion between the polymeric film and the top Ti/Pd layer is better than that between the polymer and gold (Au) and comparable to that between the polymer and an adhesion promoted Au layer. Use of the TCT metallization also results in additional cost reduction due to the elimination of Ni and Au layers on top of the Cu layer.

Abstract: Multilayer circuit devices include a plurality of metallized patterns thereon, said patterns being separated by a polymeric dielectric film. The various metallized patterns are interconnected by means of microvias through the polymeric film or films. Each of the metallizations is a composite including in succession from the substrate or from the polymeric film, a layer of titanium (Ti), a layer of titanium and palladium alloy (Ti/Pd), a layer of copper (Cu), and a layer of titanium and palladium alloy (Ti/Pd). The Ti--Ti/Pd--Cu--Ti/Pd composite is hereinafter referred to as TCT. The adhesion between the polymeric film and the top Ti/Pd layer is better than that between the polymer and gold (Au) and comparable to that between the polymer and an adhesion promoted Au layer. Use of the TCT metallization also results in additional cost reduction due to the elimination of Ni and Au layers on top of the Cu layer.