Abstract: A technique is disclosed for calibration of read voltages in a memory device. In some instances, a controller, measures a read level corresponding to a predetermined voltage applied to an array of the memory device. The controller computes a rolling average read level measurement based on the read level and a previously computed rolling average read level measurement. The controller assigns the array to a respective bin of bins to identify one or more read voltages for use by the controller to read data from the array. The controller can record the computed rolling average read level measurement in memory for use in a subsequent rolling average read level measurement computation to replace the previously computed rolling average read level measurement.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initiate a scan operation on a plurality of block families of the memory device. Each of the plurality of block families is assigned to a voltage offset bin of a plurality of voltage offset bins. The processing device further determines that a number of scan operations to be performed in one scan interval is greater than a maximum number of scan operations to be performed in a scan interval. The processing device further determines based on the voltage offset bins of the plurality of block families and a time elapsed since execution of a previous scan operation of the plurality of block families, a scan priority of each of the plurality of block families, and schedules, based on the scan priority, a scan operation of one or more block families of the plurality of block families during one or more subsequent scan intervals.

Abstract: For each voltage offset bin of a plurality of voltage offset bins, a corresponding period of scan operations of memory blocks associated with the voltage offset bin is determined. For each voltage offset bin of the plurality of voltage offset bins, a corresponding scheduling time offset of scan operations is determined. For a chosen voltage offset bin, based on a period of scan operations associated with the chosen voltage offset bin and a scheduling time offset associated with the chosen voltage offset bin, a scan operation is scheduled. The scan operation with respect to one or more blocks associated with the chosen voltage offset bin is performed.

Abstract: A method for generating a virtual block stripe in a memory device is described. The method includes determining a minimum quantity of data blocks in the virtual block stripe to be generated and determining that a first bank has a first quantity of operational data blocks that is greater than the minimum quantity of data blocks in the virtual block stripe. The method also includes determining that a second bank has a second quantity of operational data blocks that is less than the minimum quantity of data blocks in the virtual block stripe and logically mapping one or more data blocks of the first bank to the second bank. The method further includes generating the virtual block stripe comprising the second quantity of operational data blocks of the second bank and the logically mapped one or more data blocks of the first bank.

Abstract: A processing device in a memory sub-system determines a current temperature of a memory device and accesses historical transition data for management units at a plurality of temperatures. The processing device determines a transition time based on the historical transition data and current temperature, sets a scan frequency based on the transition time, and traverses management units at the scan frequency to maintain the management units in a transient state with lower raw bit error rate. The scan frequency may be set to be less than the transition time to prevent management units from transitioning to a stable state with higher raw bit error rate.

Abstract: A processing device determines, during a pre-runtime stage associated with a memory device, a first relationship comprising a first modeling of a first parameter of the memory device and a second parameter of the memory device. During the pre-runtime stage, a grown bad block allowance is determined based on the first relationship associated with the memory device. The grown bad blocks allowance is stored in a storage location associated with the memory device, where the memory device uses the grown bad blocks allowance during runtime.

Abstract: Processing logic of a memory sub-system to measure a set of slow charge loss (SCL) values, wherein each SCL value of the set of slow charge loss values corresponds to a memory die of a set of memory dies of a memory sub-system. An ordered SCL index based on the set of SCL values is generated. Using a die family threshold level, a set of ranges of the ordered SCL index is identified. Each range of the set of ranges is assigned to a corresponding die family of a set of die families.

Abstract: Methods, systems, and apparatuses include probabilistically determining a read operation number using a window size. A read command is received from a host device by a memory subsystem. A memory address is determined using the read command. It is determined that the read command corresponds to the read operation number. The memory address is flagged to have a select gate of the memory address scanned. The select gate of the memory address is scanned in response to flagging the memory address.

Abstract: Various aspects of the present disclosure relate to a memory sub-system for migrating data based on wordline information. A processing device received data from a host system and writes the data to a first memory portion of the memory device. The processing device determines to move at least a subset of data stored in the first memory portion of the memory device to a second memory portion of the memory device configured as multiple-level cell (XLC) memory, the subset of data being associated with a first wordline of the plurality of wordlines. The processing device obtains information associated with a second wordline of the plurality of wordlines, the second wordline being adjacent to the first wordline. The processing device performs a data migration operation, using the information associated with the second wordline, to move the subset of data from the first memory portion to the second memory portion.

Abstract: Methods, systems, and devices for redundant array of independent not-AND (RAIN) block retirement handling are described. A memory system may implement techniques to avoid the preemptive retirement of a block of a memory device. In some examples, the memory system may count a quantity of bit errors for each block while performing a recovery procedure, such as a RAIN procedure. The memory system may determine that the quantity of bit errors satisfies a threshold for multiple blocks, which indicate that the error that triggered the recovery procedure may have been caused by intrinsic stress at the memory system, and the memory system may refrain from retiring the block. In some examples, the memory system may compare the corrected data with raw data read using stored read settings from a failed read operation, and the memory system may determine whether to retire the block based on the comparison.

Abstract: A system includes a memory device with multiple cells and a processing device to perform operations including: identifying a group of wordlines, each connected to a subset of cells, and assigning a specified charge loss classification value to that group. The operations can also include selecting a page level, selecting a first set of cells, determining, for the first set of cells, a value of a first data state metric, identifying a second set of cells charged to a specified charge state, and determining a value of a second data state metric. The operations can also include maintaining a skew counter of the second data state metric, identifying and updating a read reference voltage offset, as well as applying the updated read reference voltage offset in a read operation.

Abstract: Methods, apparatuses and systems related to calibrating a processing level used for one or more memory operations are described. An apparatus may include a calibration mechanism that iteratively updates the processing level based on obtaining (1) base feedback from using the processing level for a memory operation and (2) at least one offset feedback from using an offset level for the memory operation. The apparatus can iteratively adjust the processing level until the base feedback, the at least one offset feedback, or a combination thereof are below a feedback threshold.

Abstract: A processing device in a memory sub-system traverses a plurality of management units of a memory device at a defined scan/read refresh frequency. For every management unit of the plurality of management units, the processing device identifies a page satisfying a lowest sensing overhead criterion, and senses data of the identified page without transferring the data out of the memory device. A non-transitory computer readable medium includes program instructions that when executed by a processing device, cause the processing device to perform operations of traversing a plurality of management units of a memory device at a defined scan/read refresh frequency. For every management unit, the processing device identifies a page satisfying a lowest sensing overhead criterion, and senses data of the identified page without transferring the data out of the memory device.

Abstract: The present disclosure configures a system component, such as a memory sub-system controller, to provide adaptive media management based on bit error rates. The controller receives a request to read data from an individual memory component of a set of memory components and, in response to receiving the request to read the data, reads the data from the individual memory component. The controller computes a number of errors associated with reading the data from the individual memory component. The controller determines whether the number of errors satisfies a refresh condition and selectively refreshes the data stored in the individual memory component based on whether the number of errors satisfies the refresh condition.

Abstract: A system includes a memory device with multiple cells and a processing device to perform operations including: identifying a group of wordlines, each connected to a subset of cells, and assigning a specified charge loss classification value to that group. The operations can also include selecting a page level, selecting a first set of cells, determining, for the first set of cells, a value of a first data state metric, identifying a second set of cells charged to a specified charge state, and determining a value of a second data state metric. The operations can also include maintaining a skew counter of the second data state metric, identifying and updating a read reference voltage offset, as well as applying the updated read reference voltage offset in a read operation.

Abstract: A system includes a memory device and a processing device operatively coupled to the memory device. The processing device is to perform operations including determining that a scan triggering condition has been satisfied for a block of the memory device. The operations further include setting a scan flag associated with the block to a first value indicative of satisfaction of the scan triggering condition. The operations further include delaying a scan operation of the block until an erase operation is performed on the block. The operations further include, responsive to performing the erase operation on the block, performing the scan operation on the block. The operations further include setting the scan flag associated with the block to a second value.

Abstract: This disclosure configures a memory sub-system controller to dynamically perform read disturb scan operations. The controller reads data from an individual page stored on an individual memory component using a first set of read levels. The controller determines that a first error rate associated with reading the data from the individual page using the first set of read levels is greater than a first threshold. The controller reads the data from the individual page using a second set of read levels different from the first set of read levels. The controller selectively folds the individual page stored on the individual memory component based on a second error rate associated with reading the data from the individual page using the second set of read levels.

Abstract: An example method comprises: identifying, by a processing device, among a plurality of wordlines of a memory device, a first subset of ordinary wordlines and a second subset of mandatory wordlines, wherein a mandatory wordline of the second subset exhibits a first value of a data state metric that exceeds a second value of the data state metric exhibited by an ordinary wordline of the first subset; performing a media scan operation with respect to a plurality of memory pages addressable by the mandatory wordline, wherein each page of the plurality of memory pages is contained by a respective management unit; and responsive to determining that a value of the data state metric of a memory page of the plurality of memory pages addressable by the mandatory wordline satisfies a specified condition, performing a media management operation with respect to a management unit containing the memory page.

Abstract: A processing device in a memory sub-system performs a first media scan operation with respect to a plurality of memory pages addressable by the ordinary wordline, wherein each page of the plurality of memory pages is contained by a respective management unit, and responsive to determining that a value of a data state metric of a memory page of the plurality of memory page addressable by the ordinary wordline satisfies a specified condition, performs a first media management operation with respect to a management unit containing the memory page.

Abstract: A system and/or method uses a trained U-Net neural network to remove flow artifacts from optical coherence tomography (OCT) angiography (OCTA) data. The trained U-Net receives as input both OCT structural volume data and OCTA volume data, but expands the OCTA volume data to include depth information. The U-Net applies dynamic pooling along the depth direction and weighs more heavily the portion of the data that follows (e.g., along the contours of) select retinal layers. In this manner the U-Net applies contextually different computations at different axial locations based at least in part on the depth index information and/or (e.g., proximity to) the select retinal layers. The U-net outputs OCT volume data of reduced flow artifacts as compared with the input OCTA data.