Abstract: Methods, systems, and apparatuses include probabilistically determining a read operation number using a window size. A read command is received from a host device by a memory subsystem. A memory address is determined using the read command. It is determined that the read command corresponds to the read operation number. The memory address is flagged to have a select gate of the memory address scanned. The select gate of the memory address is scanned in response to flagging the memory address.

Abstract: A processing device determines, during a pre-runtime stage associated with a memory device, a first relationship comprising a first modeling of a first parameter of the memory device and a second parameter of the memory device. During the pre-runtime stage, a grown bad block allowance is determined based on the first relationship associated with the memory device. The grown bad blocks allowance is stored in a storage location associated with the memory device, where the memory device uses the grown bad blocks allowance during runtime.

Abstract: For each voltage offset bin of a plurality of voltage offset bins, a corresponding period of scan operations of memory blocks associated with the voltage offset bin is determined. For each voltage offset bin of the plurality of voltage offset bins, a corresponding scheduling time offset of scan operations is determined. For a chosen voltage offset bin, based on a period of scan operations associated with the chosen voltage offset bin and a scheduling time offset associated with the chosen voltage offset bin, a scan operation is scheduled. The scan operation with respect to one or more blocks associated with the chosen voltage offset bin is performed.

Abstract: A processing device, operatively coupled with a memory device, performs a first programming operation on a first set of cells addressable by a first wordline of a first plane of the memory device. The processing device identifies a predefined index shift value associated with the first wordline. The processing device determines, by applying the predefined index shift value to a first index value of the first wordline, a second index value of a second wordline of a second plane of the memory device. The processing device further performs a second programming operation on a second set of cells addressable by the second wordline of the second plane.

Abstract: An optoelectronic device controller includes a first circuit configurable to generate a pulse width modulation signal based at least in part on (i) an adjustable threshold voltage and (ii) a periodic waveform, and a second circuit configurable to modulate light output of an optoelectronic device based at least in part on the pulse width modulation signal. The periodic waveform may be an output of a triangle wave generator. The optoelectronic device may be one of a laser and a light-emitting diode.

Abstract: In some embodiments, a computer-implemented method of predicting a molecule type using segment read information is provided. A computing device receives a segment read for a molecule. The computing device determines one or more k-mers for the segment read. For each k-mer of the one or more k-mers, the computing device retrieves one or more records from a hash table using the k-mer as a key, wherein each record includes an identifier associated with a molecule type. The computing device generates a molecule type prediction for the segment read based on the identifiers of the retrieved one or more records.

Abstract: A method for generating a virtual block stripe in a memory device is described. The method includes determining a minimum quantity of data blocks in the virtual block stripe to be generated and determining that a first bank has a first quantity of operational data blocks that is greater than the minimum quantity of data blocks in the virtual block stripe. The method also includes determining that a second bank has a second quantity of operational data blocks that is less than the minimum quantity of data blocks in the virtual block stripe and logically mapping one or more data blocks of the first bank to the second bank. The method further includes generating the virtual block stripe comprising the second quantity of operational data blocks of the second bank and the logically mapped one or more data blocks of the first bank.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initiate a scan operation on a plurality of block families of the memory device. Each of the plurality of block families is assigned to a voltage offset bin of a plurality of voltage offset bins. The processing device further determines that a number of scan operations to be performed in one scan interval is greater than a maximum number of scan operations to be performed in a scan interval. The processing device further determines based on the voltage offset bins of the plurality of block families and a time elapsed since execution of a previous scan operation of the plurality of block families, a scan priority of each of the plurality of block families, and schedules, based on the scan priority, a scan operation of one or more block families of the plurality of block families during one or more subsequent scan intervals.

Abstract: Methods, systems, and apparatuses include probabilistically determining a read operation number using a window size. A read command is received from a host device by a memory subsystem. A memory address is determined using the read command. It is determined that the read command corresponds to the read operation number. The memory address is flagged to have a select gate of the memory address scanned. The select gate of the memory address is scanned in response to flagging the memory address.

Abstract: For each voltage offset bin of a plurality of voltage offset bins, a corresponding period of scan operations of memory blocks associated with the voltage offset bin is determined. For each voltage offset bin of the plurality of voltage offset bins, a corresponding scheduling time offset of scan operations is determined. For a chosen voltage offset bin, based on a period of scan operations associated with the chosen voltage offset bin and a scheduling time offset associated with the chosen voltage offset bin, a scan operation is scheduled. The scan operation with respect to one or more blocks associated with the chosen voltage offset bin is performed.

Abstract: Processing logic of a memory sub-system to measure a set of slow charge loss (SCL) values, wherein each SCL value of the set of slow charge loss values corresponds to a memory die of a set of memory dies of a memory sub-system. An ordered SCL index based on the set of SCL values is generated. Using a die family threshold level, a set of ranges of the ordered SCL index is identified. Each range of the set of ranges is assigned to a corresponding die family of a set of die families.

Abstract: A measure associated with a characteristic of each die of a plurality of dies of a memory device is obtained. A die family distribution policy is identified. The die family distribution policy indicates a size capacity for each die family of a plurality of die families. The size capacity corresponds to the measure of each die. Each die of the plurality of dies is associated with a die family of the plurality of die families according to the die family distribution policy.

Abstract: A technique is disclosed for calibration of read voltages in a memory device. In some instances, a controller, measures a read level corresponding to a predetermined voltage applied to an array of the memory device. The controller computes a rolling average read level measurement based on the read level and a previously computed rolling average read level measurement. The controller assigns the array to a respective bin of bins to identify one or more read voltages for use by the controller to read data from the array. The controller can record the computed rolling average read level measurement in memory for use in a subsequent rolling average read level measurement computation to replace the previously computed rolling average read level measurement.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initiate a scan operation on a plurality of block families of the memory device. Each of the plurality of block families is assigned to a voltage offset bin of a plurality of voltage offset bins. The processing device further determines that a number of scan operations to be performed in one scan interval is greater than a maximum number of scan operations to be performed in a scan interval. The processing device further determines based on the voltage offset bins of the plurality of block families and a time elapsed since execution of a previous scan operation of the plurality of block families, a scan priority of each of the plurality of block families, and schedules, based on the scan priority, a scan operation of one or more block families of the plurality of block families during one or more subsequent scan intervals.

Abstract: For each voltage offset bin of a plurality of voltage offset bins, a corresponding period of scan operations of memory blocks associated with the voltage offset bin is determined. For each voltage offset bin of the plurality of voltage offset bins, a corresponding scheduling time offset of scan operations is determined. For a chosen voltage offset bin, based on a period of scan operations associated with the chosen voltage offset bin and a scheduling time offset associated with the chosen voltage offset bin, a scan operation is scheduled. The scan operation with respect to one or more blocks associated with the chosen voltage offset bin is performed.

Abstract: A method for generating a virtual block stripe in a memory device is described. The method includes determining a minimum quantity of data blocks in the virtual block stripe to be generated and determining that a first bank has a first quantity of operational data blocks that is greater than the minimum quantity of data blocks in the virtual block stripe. The method also includes determining that a second bank has a second quantity of operational data blocks that is less than the minimum quantity of data blocks in the virtual block stripe and logically mapping one or more data blocks of the first bank to the second bank. The method further includes generating the virtual block stripe comprising the second quantity of operational data blocks of the second bank and the logically mapped one or more data blocks of the first bank.

Abstract: A processing device in a memory sub-system determines a current temperature of a memory device and accesses historical transition data for management units at a plurality of temperatures. The processing device determines a transition time based on the historical transition data and current temperature, sets a scan frequency based on the transition time, and traverses management units at the scan frequency to maintain the management units in a transient state with lower raw bit error rate. The scan frequency may be set to be less than the transition time to prevent management units from transitioning to a stable state with higher raw bit error rate.

Abstract: Processing logic of a memory sub-system to measure a set of slow charge loss (SCL) values, wherein each SCL value of the set of slow charge loss values corresponds to a memory die of a set of memory dies of a memory sub-system. An ordered SCL index based on the set of SCL values is generated. Using a die family threshold level, a set of ranges of the ordered SCL index is identified. Each range of the set of ranges is assigned to a corresponding die family of a set of die families.

Abstract: A processing device determines, during a pre-runtime stage associated with a memory device, a first relationship comprising a first modeling of a first parameter of the memory device and a second parameter of the memory device. During the pre-runtime stage, a grown bad block allowance is determined based on the first relationship associated with the memory device. The grown bad blocks allowance is stored in a storage location associated with the memory device, where the memory device uses the grown bad blocks allowance during runtime.

Abstract: Methods, systems, and apparatuses include probabilistically determining a read operation number using a window size. A read command is received from a host device by a memory subsystem. A memory address is determined using the read command. It is determined that the read command corresponds to the read operation number. The memory address is flagged to have a select gate of the memory address scanned. The select gate of the memory address is scanned in response to flagging the memory address.