Abstract: There is disclosed an integrated circuit including a digital processor having EEPROM and a control register. The digital processor is capable of receiving data to be programmed into the EEPROM and is capable of programming the data into the EEPROM. The digital processor includes a control register for receiving bits to control a write line and an erase line. The digital processor also includes a processor core coupled to the control register by a data bus, the digital processor is coupled to the EEPROM by a ROM address bus and a RAM data bus. The EEPROM memory location identified by the ROM address bus is programmed to retain data latched onto the RAM data bus. This is achieved by the digital processor writing control bits to the control register to enable the write line for a write operation of sufficient duration to assure that the data on the RAM data bus is retained in the EEPROM memory address that is enabled.