Abstract: An apparatus, system, and method are disclosed for caching fully buffered memory (FBM) data. A circuit card is connected to an FBM socket that is configured to receive a FBM. An interface module communicates with a memory controller and at least one FBM via the FBM socket through a plurality of electrical interfaces. A cache controller apportions memory space in the cache memory between each FBM of the at least one FBM according to an apportionment policy. A cache memory transparently stores data from the at least one FBM and the memory controller and transparently provides the data to the memory controller. The cache controller manages coherency between the at least one FBM and the cache memory.