Patents by Inventor Aaron Morrow

Aaron Morrow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145557
    Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Inventors: Ehren MANNEBACH, Aaron LILAK, Hui Jae YOO, Patrick MORROW, Anh PHAN, Willy RACHMADY, Cheng-Ying HUANG, Gilbert DEWEY
  • Patent number: 11942416
    Abstract: Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: March 26, 2024
    Assignee: Intel Corporation
    Inventors: Ehren Mannebach, Aaron Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan, Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey, Rishabh Mehandru
  • Patent number: 11935933
    Abstract: An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.
    Type: Grant
    Filed: April 5, 2023
    Date of Patent: March 19, 2024
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Rishabh Mehandru, Aaron D. Lilak, Kimin Jun
  • Patent number: 11935891
    Abstract: Multiple non-silicon semiconductor material layers may be stacked within a fin structure. The multiple non-silicon semiconductor material layers may include one or more layers that are suitable for P-type transistors. The multiple non-silicon semiconductor material layers may further include one or more one or more layers that are suited for N-type transistors. The multiple non-silicon semiconductor material layers may further include one or more intervening layers separating the N-type from the P-type layers. The intervening layers may be at least partially sacrificial, for example to allow one or more of a gate, source, or drain to wrap completely around a channel region of one or more of the N-type and P-type transistors.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: March 19, 2024
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Patrick Morrow, Ravi Pillarisetty, Rishabh Mehandru, Cheng-ying Huang, Willy Rachmady, Aaron Lilak
  • Patent number: 11916118
    Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.
    Type: Grant
    Filed: April 4, 2023
    Date of Patent: February 27, 2024
    Assignee: Intel Corporation
    Inventors: Ehren Mannebach, Aaron Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan, Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey
  • Patent number: 11151505
    Abstract: A device may receive data associated with one or more healthcare organizations. The data may relate to a performance of one or more processes or operations of the one or more healthcare organizations. The device may process the data using one or more techniques to permit mapping of the data to a healthcare operating model. The device may map the data to the healthcare operating model. The healthcare operating model may be used to perform one or more analyses of the one or more processes or operations of the one or more healthcare organizations. The device may perform one or more analyses of the data to identify one or more deficiencies related to the one or more processes or operations. The device may perform one or more actions to positively impact the performance of the one or more processes or operations of the one or more healthcare organizations.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: October 19, 2021
    Assignee: Accenture Global Solutions Limited
    Inventors: RaeAnn J. Hancock, Scott Alister, Marjorie P. Bogaert, Denise M. Brock, Amber Brockington, Doreen Colburn, Aakash R. Desai, John M. Froehlich, Betty J. Gillespie, Ninad Gokhale, Amit Jindal, Daniel Huedig, Brian P. Kalis, Franklin C. Lee, Thomas N. Mangan, Gerald J. Meklaus, Aaron Morrow, Jennifer Nichol, Milind Pawar, Douglas Pedersen, Frank Pino, Ann Turner, Cristi Velastegui, Joseph Wee