Patents by Inventor Aaron Nygren
Aaron Nygren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10482043Abstract: A memory module includes a memory, a cache to cache copies of information stored in the memory, and a controller. The controller is configured to access first data from the memory or the cache in response to receiving a read request from a processor. The controller is also configured to transmit a first signal a first nondeterministic time interval after receiving the read request. The first signal indicates that the first data is available. The controller is further configured to transmit a second signal a first deterministic time interval after receiving a first transmit request from the processor in response to the first signal. The second signal includes the first data. The memory module also includes a buffer to store a write request until completion and a counter that is incremented in response to receiving the write request and decremented in response to completing the write request.Type: GrantFiled: July 28, 2017Date of Patent: November 19, 2019Assignee: Advanced Micro Devices, Inc.Inventors: Aaron Nygren, Michael Ignatowski, David A. Roberts
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Publication number: 20180060257Abstract: A memory module includes a memory, a cache to cache copies of information stored in the memory, and a controller. The controller is configured to access first data from the memory or the cache in response to receiving a read request from a processor. The controller is also configured to transmit a first signal a first nondeterministic time interval after receiving the read request. The first signal indicates that the first data is available. The controller is further configured to transmit a second signal a first deterministic time interval after receiving a first transmit request from the processor in response to the first signal. The second signal includes the first data. The memory module also includes a buffer to store a write request until completion and a counter that is incremented in response to receiving the write request and decremented in response to completing the write request.Type: ApplicationFiled: July 28, 2017Publication date: March 1, 2018Inventors: Aaron NYGREN, Michael IGNATOWSKI, David A. ROBERTS
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Patent number: 8782458Abstract: A system and method of data communications between a first device and a second device is disclosed. The method includes generating a first clock signal at the first device and generating a second clock signal having a phase offset from the first clock signal. The clock signals are transmitted from the first device to the second device. The method further includes regulating transmission of a read strobe signal sent from the second device to the first device utilizing the first clock signal. The method also includes regulating transmission of a data transfer signal sent from the second device to the first device utilizing the second clock signal.Type: GrantFiled: November 29, 2011Date of Patent: July 15, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Aaron Nygren, Anwar Kashem, Edoardo Prete, Gerry Talbot
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Patent number: 8726139Abstract: Provided herein is a method and system for providing and analyzing unified data signaling that includes setting, or analyzing a state of a single indicator signal, generating or analyzing a data pattern of a plurality of data bits, and signal, or determine, based on the state of the single indicator signal and the pattern of the plurality of data bits, that data bus inversion has been applied to the plurality of data bits or that the plurality of data bits is poisoned.Type: GrantFiled: December 14, 2011Date of Patent: May 13, 2014Assignee: Advanced Micro Devices, Inc.Inventors: James O'Connor, Aaron Nygren, Anwar Kashem, Warren Fritz Kruger, Bryan Black
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Publication number: 20130159587Abstract: A multi-interconnect integrated circuit device includes an input/output (I/O) circuit for conveying a plurality of interleaved data channel groups by configuring the I/O circuit to convey a first data channel group over a default fixed interconnect signal paths if there are no connection failures in the default fixed interconnect signal paths, and to convey the first data channel group over a second plurality of default fixed interconnect signal paths if there is at least one connection failure in the first plurality of default fixed interconnect signal paths, where the second plurality of default fixed interconnect signal paths includes a redundant fixed interconnect signal path for replacing a failed interconnect signal path from the first plurality of default fixed interconnect signal paths.Type: ApplicationFiled: December 15, 2011Publication date: June 20, 2013Inventors: Aaron Nygren, Anwar Kashem, Bryan Black, James Michael O'Connor, Warren F. Kruger
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Publication number: 20130159818Abstract: Provided herein is a method and system for providing and analyzing unified data signaling that includes setting, or analyzing a state of a single indicator signal, generating or analyzing a data pattern of a plurality of data bits, and signal, or determine, based on the state of the single indicator signal and the pattern of the plurality of data bits, that data bus inversion has been applied to the plurality of data bits or that the plurality of data bits is poisoned.Type: ApplicationFiled: December 14, 2011Publication date: June 20, 2013Applicant: Advanced Micro Devices, Inc.Inventors: James O'Connor, Aaron Nygren, Anwar Kashem, Warren Fritz Kruger, Bryan Black
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Publication number: 20130136195Abstract: A system and method of data communications between a first device and a second device is disclosed. The method includes generating a first clock signal at the first device and generating a second clock signal having a phase offset from the first clock signal. The clock signals are transmitted from the first device to the second device. The method further includes regulating transmission of a read strobe signal sent from the second device to the first device utilizing the first clock signal. The method also includes regulating transmission of a data transfer signal sent from the second device to the first device utilizing the second clock signal.Type: ApplicationFiled: November 29, 2011Publication date: May 30, 2013Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Aaron Nygren, Anwar Kashem, Edoardo Prete, Gerry Talbot
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Patent number: 8443225Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.Type: GrantFiled: August 13, 2012Date of Patent: May 14, 2013Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Aaron Nygren, Ming-Ju Edward Lee, Shadi Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger, Michael Litt
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Publication number: 20120303995Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.Type: ApplicationFiled: August 13, 2012Publication date: November 29, 2012Applicants: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Aaron Nygren, Ming-Ju Edward Lee, Shadi Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger, Michael Litt
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Patent number: 8245073Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.Type: GrantFiled: July 24, 2009Date of Patent: August 14, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Aaron Nygren, Ming-Ju Edward Lee, Shadi Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger, Michael Litt
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Patent number: 8161344Abstract: A description is given of a circuit for creating an error coding data block for a first data block, including a first error coding path adapted to create the error coding data block in accordance with a first error coding; and a second error coding path adapted to create the error coding data block in accordance with a second error coding; the error coding data block for the first data block being created optionally by the first or second error coding paths, as a function of a control indicator, and at least the first error coding path comprising a data arrangement alteration device.Type: GrantFiled: March 11, 2008Date of Patent: April 17, 2012Assignee: Qimonda AGInventor: Aaron Nygren
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Publication number: 20110019787Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.Type: ApplicationFiled: July 24, 2009Publication date: January 27, 2011Inventors: Aaron Nygren, Ming-Ju Edward Lee, Shadi Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger, Michael Litt
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Patent number: 7440349Abstract: An integrated semiconductor memory capable of determining a chip temperature includes first control terminals for driving the integrated semiconductor memory with first control signals for performing a write access and second control terminals provided for performing a read access. The integrated semiconductor further includes a control circuit for controlling a write and read access. A temperature sensor for recording a chip temperature of the integrated semiconductor memory is connected to the control circuit. The control circuit is configured to generate a state of a third control signal at one of the first or at one of the second control terminals in a manner dependent on a temperature recorded by the temperature sensor.Type: GrantFiled: December 7, 2006Date of Patent: October 21, 2008Assignee: Qimonda AGInventors: Georg Braun, Aaron Nygren
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Publication number: 20080244358Abstract: A description is given of a circuit for creating an error coding data block for a first data block, including a first error coding path adapted to create the error coding data block in accordance with a first error coding; and a second error coding path adapted to create the error coding data block in accordance with a second error coding; the error coding data block for the first data block being created optionally by the first or second error coding paths, as a function of a control indicator, and at least the first error coding path comprising a data arrangement alteration device.Type: ApplicationFiled: March 11, 2008Publication date: October 2, 2008Inventor: Aaron Nygren
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Publication number: 20080198666Abstract: A semiconductor device is disclosed. In one embodiment, the device includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to drive output signals and includes an adjustable output impedance. The second circuit is configured to adjust the adjustable output impedance. The third circuit is configured to sense a first parameter and to activate the second circuit to adjust the adjustable output impedance based on changes in the first parameter exceeding a first threshold value.Type: ApplicationFiled: February 20, 2007Publication date: August 21, 2008Inventor: Aaron Nygren
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Circuit arrangement and method for converting logic signal levels and use of the circuit arrangement
Patent number: 7414435Abstract: A circuit arrangement for converting logic signal levels has a level converter and a mixing arrangement for influencing a pulse width. The level converter includes a first signal path and a second signal path each having a series circuit comprising two transistors of different conductivity types and two outputs which are each connected to a tap between the transistors which are coupled in series. In this case, the transistors of one conductivity type can be controlled by means of a push-pull signal and the transistors of the other conductivity type in a respective one of the two signal paths can be controlled by means of a signal at the output of the respective other signal path. The mixing arrangement includes two inputs and two outputs, the first input being coupled to the first output and the second input being coupled to the second output.Type: GrantFiled: December 13, 2006Date of Patent: August 19, 2008Assignee: Qimonda AGInventors: Maksim Kuzmenka, Aaron Nygren -
Patent number: 7391245Abstract: A delay locked loop includes a delay chain that contains a plurality of series-connected delay cells, a phase detector arrangement that contains a plurality of phase detector cells and a control unit. The delay locked loop delays an input signal by a delay time via the delay chain depending on the number of delay cells in the series that are activated for delay. The phase detector arrangement detects the phase of the signal at the output of each delay cell in the delay chain. The control unit activates a number Z of the delay cells of the delay chain based on the difference in phase of the original signal and the delayed signal.Type: GrantFiled: May 22, 2006Date of Patent: June 24, 2008Assignee: Infineon Technologies AGInventors: Patrick Heyne, Aaron Nygren
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Output driver circuit and a method of transmitting an electrical signal via an output driver circuit
Patent number: 7355458Abstract: In an output driver circuit, the signal propagation time of an electrical signal which is to be transmitted between two selected driver stages is ascertained. If the ascertained signal propagation time is at least equal to half the period duration of the signal which is to be transmitted, the signal to be transmitted is delayed between the two selected driver stages such that a given signal edge change appears at the output of the other of the selected driver stages at a different time from other signal edge which follow the one given signal edge change in time, at driver stages which are situated upstream of the other of the selected driver stages. The inventive output driver circuit accordingly has a delay element which can be used to influence the signal propagation time between the selected driver stages.Type: GrantFiled: November 22, 2005Date of Patent: April 8, 2008Assignee: Infineon Technologies, AGInventors: Aaron Nygren, Maksim Kuzmenka -
Circuit arrangement and method for converting logic signal levels and use of the circuit arrangement
Publication number: 20080054940Abstract: A circuit arrangement for converting logic signal levels has a level converter and a mixing arrangement for influencing a pulse width. The level converter includes a first signal path and a second signal path each having a series circuit comprising two transistors of different conductivity types and two outputs which are each connected to a tap between the transistors which are coupled in series. In this case, the transistors of one conductivity type can be controlled by means of a push-pull signal and the transistors of the other conductivity type in a respective one of the two signal paths can be controlled by means of a signal at the output of the respective other signal path. The mixing arrangement includes two inputs and two outputs, the first input being coupled to the first output and the second input being coupled to the second output.Type: ApplicationFiled: December 13, 2006Publication date: March 6, 2008Inventors: Maksim Kuzmenka, Aaron Nygren -
Patent number: 7304495Abstract: A driver system, a driver calibration circuit arrangement for calibration of an impedance of a driver circuit arrangement, and a method for calibration of an impedance of a driver circuit arrangement can achieve improved driver behavior, with respect to undesirable distortions of the slew rate caused by off-chip drivers of DDR memory modules. A driver system has a first driver part with at least one variable impedance by which an operating point of the first driver part is determined with respect to a first potential and a second potential. The potentials supply the first driver part. A first monitoring device adjusts an impedance value of the variable impedance such that the operating point differs from a mid-point of the first and of the second potential.Type: GrantFiled: October 29, 2004Date of Patent: December 4, 2007Assignee: Infineon Technologies AGInventor: Aaron Nygren