Patents by Inventor Aaron Paul Hurst

Aaron Paul Hurst has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9411912
    Abstract: In one embodiment of the invention, a method of physical clock topology planning for designing integrated circuits is disclosed. The method includes reading an initial placed netlist of an integrated circuit design and a floorplan of the integrated circuit design, analyzing the integrated circuit design to determine potential enable signals to gate clock signals that clock the plurality of flip flops to reduce power consumption; simultaneously optimizing and placing the clock enable logic gates to gate clock signals to the plurality of flip flops; and minimizing timing variation of the clock signals to the plurality of flip flops.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 9, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ankush Sood, Aaron Paul Hurst
  • Patent number: 9280614
    Abstract: In one embodiment of the invention, a method of physical clock topology planning for designing integrated circuits is disclosed. The method includes reading an initial placed netlist of an integrated circuit design and a floorplan of the integrated circuit design, analyzing the integrated circuit design to determine potential enable signals to gate clock signals that clock the plurality of flip flops to reduce power consumption; simultaneously optimizing and placing the clock enable logic gates to gate clock signals to the plurality of flip flops; and minimizing timing variation of the clock signals to the plurality of flip flops.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 8, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ankush Sood, Aaron Paul Hurst
  • Patent number: 9135375
    Abstract: In one embodiment of the invention, a method of physical clock topology planning for designing integrated circuits is disclosed. The method includes reading an initial placed netlist of an integrated circuit design and a floorplan of the integrated circuit design, analyzing the integrated circuit design to determine potential enable signals to gate clock signals that clock the plurality of flip flops to reduce power consumption; simultaneously optimizing and placing the clock enable logic gates to gate clock signals to the plurality of flip flops; and minimizing timing variation of the clock signals to the plurality of flip flops.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 15, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ankush Sood, Aaron Paul Hurst
  • Patent number: 8826211
    Abstract: In one embodiment of the invention, a method for displaying and analyzing a clock gate tree topology is disclosed. The method includes displaying a bounding box of each flip-flop cluster in the floor plan of the integrated circuit; and for each flip-flop cluster, calculating the coordinates for a center of mass of the flip-flop cluster, displaying the position of the clock gate driving the flip-flops in the flip-flop cluster with respect to the center of mass of the flip-flop cluster, displaying first air lines from the enable signal gate to the clock gate with a first color, and displaying second air lines from the clock gate to the center of mass of the flip-flop cluster with a second color differing from the first color.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 2, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ankush Sood, Aaron Paul Hurst