Abstract: An embodiment of the invention may include a method, computer program product, and computer system for monitoring a computing device. The embodiment includes retrieving data from physical components of the method. The embodiment includes converting the data to at least one spectral format. The embodiment includes analyzing the converted data with a spectral detector. The embodiment includes performing a remediation action of the code anomaly based on detecting a code anomaly by the spectral detector.

Abstract: The inventive mechanism determines whether memory source and destination addresses map to the same or nearly the same cache address. If they map to different addresses, then loads and stores are ordered so that loads to one cache bank are performed on the same clock cycles as the stores to another cache bank. After a group of loads and stores are completed, then load and store operations for each bank are switched. If the source and destination addresses map to nearly the same cache address and if the source address is prior to the destination address, then a group of cache lines is loaded into registers and stored to memory without any interleaving of other loads and stores. If the source and destination addresses map to the same cache location, then an initial load of data into registers is performed. After that, additional loads are interleaved with non-cache conflicting stores to move new values into memory. Thus, loads and stores to matching cache addresses are separated by time.

Abstract: The inventive mechanism determines whether memory source and destination addresses map to the same or nearly the same cache address. If they map to different addresses, then loads and stores are ordered so that loads to one cache bank are performed on the same clock cycles as the stores to another cache bank. After a group of loads and stores are completed, then load and store operations for each bank are switched. If the source and destination addresses map to nearly the same cache address and if the source address is prior to the destination address, then a group of cache lines is loaded into registers and stored to memory without any interleaving of other loads and stores. If the source and destination addresses map to the same cache location, then an initial load of data into registers is performed. After that, additional loads are interleaved with non-cache conflicting stores to move new values into memory. Thus, loads and stores to matching cache addresses are separated by time.