Abstract: Described herein are various principles for assisting in the identification of a configuration of computing device and reconfiguration of the computing device. More particularly, some of the principles relate to identifying one or more software processes configured to be executed during operation of the computing device in a usage scenario. Following operation of the computing device in the usage scenario, amounts of one or more resources consumed by each of the software processes throughout the usage scenario may also be identified. In some embodiments, once the software processes and amounts of the resource(s) consumed by the software processes have been identified, the processes and the amounts can be displayed to a user and the user may then reconfigure the computing device, such as by preventing some software processes from executing during the usage scenario or by delaying an execution of some software processes.

Abstract: Techniques for improving a troubleshooting experience by providing a common troubleshooting framework. Such a framework may enable use of common elements between troubleshooters and lead to similarities between troubleshooting packages, which may improve the user experience. Further, a framework may reduce the amount of knowledge and time necessary to create troubleshooting packages, and thus encourage increased development of these troubleshooting packages. In some implementations of the framework, a troubleshooting package may be implemented in a declarative manner that outlines/describes the problems it solves and the potential solutions to those problems. The declarative troubleshooting packages may then be provided to the troubleshooting framework and may provide direction to the framework, in that the framework may execute functions as directed by the troubleshooter.

Abstract: In a cache coherency protocol multiple conflict phases may be utilized to resolve a data request conflict condition. The multiple conflict phases may avoid buffering or stalling conflict resolution, which may reduce system inefficiencies.

Abstract: In a cache coherency protocol multiple conflict phases may be utilized to resolve a data request conflict condition. The multiple conflict phases may avoid buffering or stalling conflict resolution, which may reduce system inefficiencies.

Abstract: In a cache coherency protocol multiple conflict phases may be utilized to resolve a data request conflict condition. The multiple conflict phases may avoid buffering or stalling conflict resolution, which may reduce system inefficiencies.

Abstract: An apparatus is described that routes packets to, from, and within a socket. The apparatus includes routing components that provide different functionality based upon which socket component they are connected to. One routing component is connected to an interface that communicates with the processor core of the socket.

Abstract: Disclosed are embodiments of a method, apparatus and system for a low power state for a point-to-point link. During the low power state, the signal on both conductors of a differential transmit pair are driven to electrical idle. Analog activity detectors are enabled during the low power state and are disabled during normal power state. Exit from the low power state does not require a physical layer re-initialization sequence. Other embodiments are also described and claimed.

Abstract: Disclosed are embodiments of a method, apparatus and system for a low power state for a point-to-point link. During the low power state, the signal on both conductors of a differential transmit pair are driven to electrical idle. Analog activity detectors are enabled during the low power state and are disabled during normal power state. Exit from the low power state does not require a physical layer re-initialization sequence. Other embodiments are also described and claimed.

Abstract: Disclosed are embodiments of a method, apparatus and system for a low power state for a point-to-point link. During the low power state, the signal on both conductors of a differential transmit pair are driven to electrical idle. Analog activity detectors are enabled during the low power state and are disabled during normal power state. Exit from the low power state does not require a physical layer re-initialization sequence. Other embodiments are also described and claimed.

Abstract: In a cache coherency protocol multiple conflict phases may be utilized to resolve a data request conflict condition. The multiple conflict phases may avoid buffering or stalling conflict resolution, which may reduce system inefficiencies.

Abstract: A system and method for reduced power consumption communications over a physical interconnect is described. In an embodiment, an input/output circuit includes a port to receive a transmission unit via an interconnect, a combining module coupled to the port to append at least one of a first and a second indicator to the transmission unit, a first adder module to generate the first indicator, indicating that the transmission unit is a starting transmission unit of a set of related transmission units, a second adder module to generate the second indicator, indicating that the starting transmission unit of the set of related transmission units has already been received, and logic to determine at least one of the start and end boundaries of the set of related transmission units.

Abstract: According to one embodiment of the invention, a credit/debit flow control mechanism performs credit initialization by a combination of standard protocol level messages (e.g., one or more flits) with encoded credit return values and the use of saturating counters.

Abstract: A proposal is discussed that facilitates exchanging parameters for a link layer that allows a variable number of parameters without changing a communication protocol. Likewise, the proposal allows for both components connected via the link to negotiate values for the parameters that are exchanged without a need for external agent intervention or redundancy.

Abstract: In one embodiment, the present invention includes an apparatus that has multiple buffers, including a first buffer dedicated to a first virtual channel of a first virtual network and a second buffer shared among virtual channels of a second virtual network. The shared buffer may be implemented as a shared adaptive buffer, and the buffers can be controlled using different flow control schemes, such as on a packet and flit basis. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for receiving a first portion of a first packet at a first agent and determining whether the first portion is an interleaved portion based on a value of an interleave indicator. The interleave indicator may be sent as part of the first portion. In such manner, interleaved packets may be sent within transmission of another packet, such as a lengthy data packet, providing improved processing capabilities. Other embodiments are described and claimed.

Abstract: Systems and methods of managing a link provide for receiving a remote width capability during a link initialization, the remote width capability corresponding to a remote port. A link between a local port and the remote port is operated at a plurality of link widths in accordance with the remote width capability.

Abstract: Embodiments of the invention provide an algorithm for dividing a link into one or more reduced-width links. For one embodiment of the invention, a multiplexing scheme is employed to effect a bit transmission order required by a particular cyclic redundancy check. The multiplexed output bits are then swizzled on-chip to reduce on-board routing congestion.

Abstract: Disclosed are embodiments of a method, apparatus and system for a low power state for a point-to-point link. During the low power state, the signal on both conductors of a differential transmit pair are driven to electrical idle. Analog activity detectors are enabled during the low power state and are disabled during normal power state. Exit from the low power state does not require a physical layer re-initialization sequence. Other embodiments are also described and claimed.

Abstract: In one embodiment of the present invention, a method may include separating incoming transactions to an agent of a coherent system into at least a first channel, a second channel, and a third channel, based upon a type of the incoming transactions. The incoming transactions may be sent by a peer device coupled to the coherent system. By separating the transactions based on type, deadlocks may be avoided.

Abstract: In one embodiment of the present invention, a method includes identifying a transaction from a first processor to a second processor of a system with a transaction identifier. The transaction identifier may have a value that is less than or equal to a maximum number of outstanding transactions between the two processors. In such manner, a transaction field for the transaction identifier may be limited to n bits, where the maximum number of outstanding transactions is less than or equal to 2n. In various embodiments, such a transaction identifier combined with a source identifier and a home node identifier may form a globally unique transaction identifier.