Patents by Inventor Aaron Thean

Aaron Thean has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250081561
    Abstract: A method of preparing a semiconductor structure includes forming an insulating layer having a thickness between about 5 nm and about 100 nm on a substrate, and forming an active layer comprising a tensile-strained silicon over the insulating layer. At least a portion of the active layer is implanted with ions to render at least a portion of the active layer amorphous and reduce the tensile strain in the at least portion of the active layer. The method further includes thermally annealing the implanted portion of the active layer and recrystallizing such previously rendered amorphous portion of the active layer. A germanium condensation process is performed on the recrystallized portion of the active layer to form a SiGe material having a compressive strain. Also described are the semiconductor structures.
    Type: Application
    Filed: November 19, 2024
    Publication date: March 6, 2025
    Inventors: Bich-Yen Nguyen, Christophe Maleville, Walter Schwarzenbach, Gong Xiao, Aaron Thean, Chen Sun, Haiwen Xu
  • Patent number: 12218201
    Abstract: A semiconductor structure, including: a base substrate; an insulating layer on the base substrate, the insulating layer having a thickness between about 5 nm and about 100 nm; and an active layer comprising at least two pluralities of different volumes of semiconductor material comprising silicon, germanium, and/or silicon germanium, the active layer disposed over the insulating layer, the at least two pluralities of different volumes of semiconductor material comprising: a first plurality of volumes of semiconductor material having a tensile strain of at least about 0.6%; and a second plurality of volumes of semiconductor material having a compressive strain of at least about ?0.6%. Also described is a method of preparing a semiconductor structure and a segmented strained silicon-on-insulator device.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: February 4, 2025
    Assignees: National University of Singapore, Soitec
    Inventors: Bich-Yen Nguyen, Christophe Maleville, Walter Schwarzenbach, Gong Xiao, Aaron Thean, Chen Sun, Haiwen Xu
  • Publication number: 20220399441
    Abstract: A semiconductor structure, including: a base substrate; an insulating layer on the base substrate, the insulating layer having a thickness between about 5 nm and about 100 nm; and an active layer comprising at least two pluralities of different volumes of semiconductor material comprising silicon, germanium, and/or silicon germanium, the active layer disposed over the insulating layer, the at least two pluralities of different volumes of semiconductor material comprising: a first plurality of volumes of semiconductor material having a tensile strain of at least about 0.6%; and a second plurality of volumes of semiconductor material having a compressive strain of at least about ?0.6%. Also described is a method of preparing a semiconductor structure and a segmented strained silicon on insulator device.
    Type: Application
    Filed: June 14, 2021
    Publication date: December 15, 2022
    Inventors: Bich-Yen Nguyen, Christophe Maleville, Walter Schwarzenbach, Gong Xiao, Aaron Thean, Chen Sun, Haiwen Xu
  • Publication number: 20130233238
    Abstract: Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, the method may comprise providing a substrate comprising a first crystalline material, where the first crystalline material has a first lattice constant; providing a mask structure on the substrate, where the mask structure comprises a first level comprising a first opening extending through the first level (where a bottom of the first opening comprises the substrate), and a second level on top of the first level, where the second level comprises a plurality of second trenches positioned at a non-zero angle with respect to the first opening. The method may further comprise epitaxially growing a second crystalline material on the bottom of the first opening, where the second crystalline material has a second lattice constant different than the first lattice constant and defects in the second crystalline material are trapped in the first opening.
    Type: Application
    Filed: February 15, 2013
    Publication date: September 12, 2013
    Applicant: IMEC
    Inventors: Benjamin Vincent, Aaron Thean, Liesbeth Witters