Abstract: A memory device for deep neural network, DNN, accelerators, a method of fabricating a memory device for deep neural network, DNN, accelerators, a method of convoluting a kernel [A] with an input feature map [B] in a memory device for a deep neural network, DNN, accelerator, a memory device for a deep neural network, DNN, accelerator, and a deep neural network, DNN, accelerator.

Abstract: A method and system for integrity testing of sachets. The method comprises the steps of disposing at least a portion of the sachet relative to an electrode structure; applying an AC bias voltage to the electrode structure; measuring an electrical property of the portion of the sachet over a frequency range, and determining the integrity based on the measured electrical property over the frequency range.

Abstract: A semiconductor structure, including: a base substrate; an insulating layer on the base substrate, the insulating layer having a thickness between about 5 nm and about 100 nm; and an active layer comprising at least two pluralities of different volumes of semiconductor material comprising silicon, germanium, and/or silicon germanium, the active layer disposed over the insulating layer, the at least two pluralities of different volumes of semiconductor material comprising: a first plurality of volumes of semiconductor material having a tensile strain of at least about 0.6%; and a second plurality of volumes of semiconductor material having a compressive strain of at least about ?0.6%. Also described is a method of preparing a semiconductor structure and a segmented strained silicon on insulator device.

Abstract: A method and system for integrity testing of sachets. The method comprises the steps of disposing at least a portion of the sachet relative to an electrode structure; applying an AC bias voltage to the electrode structure; measuring an electrical property of the portion of the sachet over a frequency range, and determining the integrity based on the measured electrical property over the frequency range.

Abstract: Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, the method may comprise providing a substrate comprising a first crystalline material, where the first crystalline material has a first lattice constant; providing a mask structure on the substrate, where the mask structure comprises a first level comprising a first opening extending through the first level (where a bottom of the first opening comprises the substrate), and a second level on top of the first level, where the second level comprises a plurality of second trenches positioned at a non-zero angle with respect to the first opening. The method may further comprise epitaxially growing a second crystalline material on the bottom of the first opening, where the second crystalline material has a second lattice constant different than the first lattice constant and defects in the second crystalline material are trapped in the first opening.