Abstract: All feedback cycles in a circuit network which cross only non-scannable memory elements are detected in linear run time. The method models a circuit network as a directed graph, then attributes network elements so that a single feedback cycle may be found in constant time. In the breadth first version, feedback is detected by traversing at most a constant distance back to the last scannable memory element. In the depth first version, graph nodes are not FINISHED until all predecessors are FINISHED. Feedback is found immediately if a node runs into another node that is NOT—FINISHED. This feedback is illegal if both nodes are in a zone defined by the same scannable memory element. The resulting identification and removal of feedback loops crossing only non-scannable memory elements significantly reduces the subsequent complexity of test pattern generation. This ensures a faster, more reliable, and more accurate test process after circuit fabrication.

Abstract: A digital hardware system slides a sequence to be searched, such as a genome, past a query sequence, such as a DNA fragment, via shift registers. In parallel, multiple alignments between search and query sequences are compared. As each alignment consists of many elements (characters), the parallel matching process is highly accelerated over sequential element-by-element comparison. Individual element comparisons are made using equivalence operators, such as XNOR logic gates. The results of individual element comparisons are then consolidated into a single signal: “hit” or “miss”, indicating whether all the elements for the particular alignment under test matched or not. After comparison, the search sequence is shifted by a number of elements equal to the number of parallel alignments compared, and the process repeats. An additional shifting prefetch buffer increases memory efficiency by alleviating the need to fetch data every cycle.

Abstract: All feedback cycles in a circuit network which cross only non-scannable memory elements are detected in linear run time. The method models a circuit network as a directed graph, then attributes network elements so that a single feedback cycle may be found in constant time. In the breadth first version, feedback is detected by traversing at most a constant distance back to the last scannable memory element. In the depth first version, graph nodes are not FINISHED until all predecessors are FINISHED. Feedback is found immediately if a node runs into another node that is NOT_FINISHED. This feedback is illegal if both nodes are in a zone defined by the same scannable memory element. The resulting identification and removal of feedback loops crossing only non-scannable memory elements significantly reduces the subsequent complexity of test pattern generation. This ensures a faster, more reliable, and more accurate test process after circuit fabrication.

Abstract: A digital hardware system slides a sequence to be searched, such as a genome, past a query sequence, such as a DNA fragment, via shift registers. In parallel, multiple alignments between search and query sequences are compared. As each alignment consists of many elements (characters), the parallel matching process is highly accelerated over sequential element-by-element comparison. Individual element comparisons are made using equivalence operators, such as XNOR logic gates. The results of individual element comparisons are then consolidated into a single signal: “hit” or “miss”, indicating whether all the elements for the particular alignment under test matched or not. After comparison, the search sequence is shifted by a number of elements equal to the number of parallel alignments compared, and the process repeats. An additional shifting prefetch buffer increases memory efficiency by alleviating the need to fetch data every cycle.