Patents by Inventor Aaron Willey
Aaron Willey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11483185Abstract: Disclosed is an improved approach for a training approach to implement DFE for an electronic circuit. The inventive concept is particularity suitable to address, for example, circuits that implement high speed parallel data transmission protocols, such as GDDR6, that are used for graphics applications. The training scheme uses minimal hardware when compared to existing schemes by reusing calibration receiver in auto zeroing receiver as error receiver. Further it works for closed eyes by running the algorithm multiple times with gradual increase in complexity of training pattern, where DFE coefficients from previous iteration is used for the current iteration, thereby gradually opening the eye.Type: GrantFiled: April 30, 2021Date of Patent: October 25, 2022Assignee: Cadence Design Systems, Inc.Inventors: Sachin Ramesh Gugwad, Hari Anand Ravi, Aaron Willey, Thomas E. Wilson
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Patent number: 10848352Abstract: Circuits, methods and systems that are to be used for dynamically modulating a high frequency bit duration of data based on a status of one or more previous transmitted bits. One circuit comprises a first data path comprising a first input, a first buffer, and a first output connected to a first multiplexer data input. The circuit further comprises a second data path comprising a second input, a second buffer, a phase interpolator, and a second output coupled to a second multiplexer data input. The circuit further comprises a multiplexer having at least two data inputs, at least one control input, and a common output coupled to a transmitter signal line and wherein the at least one control input is operatively coupled to a generated control signal that is based on the status of one or more previous transmitted bits.Type: GrantFiled: December 24, 2019Date of Patent: November 24, 2020Assignee: Cadence Design Systems, Inc.Inventors: Balbeer Singh Rathor, Vinod Kumar, Aaron Willey
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Patent number: 10705984Abstract: Embodiments relate to systems, methods, and computer-readable media to enable design and creation of receiver circuitry. One embodiment is a receiver apparatus comprising a plurality of receiver arrangements, each receiver arrangement having a sampling circuit and a multi-stage differential amplifier connected to the sampling circuit. Each receiver arrangement is configurable via switches between an amplifying mode and an autozero mode. Control circuitry may select output data from a sampling circuit of one or more receiver arrangements that are not in autozero mode. In various embodiments, settings for individual receiver arrangements may be set based on decision feedback equalization (DFE).Type: GrantFiled: September 26, 2018Date of Patent: July 7, 2020Assignee: Cadence Design Systems, Inc.Inventors: H Md Shuaeb Fazeel, Nikhil Sawarkar, Aaron Willey, Thomas Evan Wilson
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Patent number: 10545895Abstract: Embodiments described herein relate to circuits and techniques for interfacing a microprocessor with memory devices, particularly memory devices such as DDR SDRAM in accordance with protocols such as DDR4 and DDR5. Some embodiments particularly relate to a receiver architecture for a DDR memory interface device that provides AC coupling to memory and includes auto-zeroing functionality. These and other embodiments incorporate equalization functionality such as decision feedback equalization and continuous time linear equalization.Type: GrantFiled: January 22, 2018Date of Patent: January 28, 2020Assignee: CADENCE DESIGN SYSTEMS, INC.Inventors: Aaron Willey, Hari Anand Ravi, H. Md. Shuaeb Fazeel, Thomas Evan Wilson, Moo Sung Chae
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Patent number: 10545889Abstract: Embodiments relate to systems, methods, and computer-readable media to enable design and creation of receiver circuitry. One embodiment is a receiver apparatus comprising a plurality of receiver arrangements, each receiver arrangement having a sampling circuit and a multi-stage differential amplifier connected to the sampling circuit. Each receiver arrangement is configurable via switches between an amplifying mode and an autozero mode. Control circuitry may select output data from receiver arrangements that are not in autozero mode using multiplexer circuitry. In various embodiments, settings for individual receiver arrangements may be set based on decision feedback equalization (DFE).Type: GrantFiled: December 10, 2018Date of Patent: January 28, 2020Assignee: Cadence Design Systems, Inc.Inventors: H Md Shuaeb Fazeel, Nikhil Sawarkar, Aaron Willey, Thomas Evan Wilson
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Patent number: 10250265Abstract: Once a delay locked loop has been locked to a clock signal, an omitted clock cycle is injected into the input of the delay locked loop without stopping the operation of the delay locked loop. The omitted cycle is later detected at an output of the delay locked loop, and the delay between the input and output is determined based on the time the omitted cycle requires to propagate through the delay locked loop. Once determined, the number of cycles of delay for the delay locked loop can be used in conjunction with an internal clock signal to launch data and/or data strobes from memory devices and memory controllers such that the proper phase alignment and clock cycle alignment is achieved.Type: GrantFiled: August 9, 2018Date of Patent: April 2, 2019Assignee: Everspin Technologies, Inc.Inventors: Jieming Qi, Aaron Willey
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Publication number: 20180351560Abstract: Once a delay locked loop has been locked to a clock signal, an omitted clock cycle is injected into the input of the delay locked loop without stopping the operation of the delay locked loop. The omitted cycle is later detected at an output of the delay locked loop, and the delay between the input and output is determined based on the time the omitted cycle requires to propagate through the delay locked loop. Once determined, the number of cycles of delay for the delay locked loop can be used in conjunction with an internal clock signal to launch data and/or data strobes from memory devices and memory controllers such that the proper phase alignment and clock cycle alignment is achieved.Type: ApplicationFiled: August 9, 2018Publication date: December 6, 2018Applicant: Everspin Technologies, Inc.Inventors: Jieming Qi, Aaron Willey
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Patent number: 9419628Abstract: Measurement initialization circuitry is described. Propagation of a start signal through a variable delay line may be stopped by either of two stop signals. One stop signal corresponds to a rising edge of a reference clock signal. A second stop signal corresponds to a falling edge of the reference clock signal. The start signal propagation is stopped responsive to the first to arrive of the first and second stop signals. Accordingly, in some examples, start signal propagation through a variable delay line may be stopped responsive to either a rising or falling edge of the reference clock signal.Type: GrantFiled: September 10, 2014Date of Patent: August 16, 2016Assignee: Micron Technology, Inc.Inventors: Aaron Willey, Yantao Ma
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Patent number: 9244479Abstract: Current circuits, circuits configured to provide a bias voltage, and methods for providing a bias voltage are described, including a current circuit configured to receive a reference current and having an output at which an output current is provided. One such current circuit includes a first current mirror configured to receive a first portion of the reference current and further configured to mirror the first portion of the reference current to provide a first current. The current circuit further includes a second current mirror configured to receive a second portion of the reference current and receive the first current. The second current mirror is further configured to provide a portion of the first current to the output of the current circuit as the output current and to receive another portion of the first current and mirror the same as the second portion of the reference current.Type: GrantFiled: July 31, 2014Date of Patent: January 26, 2016Assignee: Micron Technology, Inc.Inventor: Aaron Willey
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Patent number: 9225319Abstract: Clock signal timing cells, clock signal timing circuits, clock circuits, memory devices, systems, and method for altering the timing of a clock signal are disclosed. An example method for altering the timing of an output signal provided responsive to an input clock signal includes adjusting a transition of an edge of the output signal from one voltage level to another based at least in part on a bias signal. An example clock signal timing cell includes an inverter and a bias controlled inverter coupled in parallel to the inverter. The bias controlled circuit is configured to provide an output signal wherein a transition of a clock edge of the output signal between first and second voltage levels is based at least in part on a bias signal.Type: GrantFiled: February 4, 2014Date of Patent: December 29, 2015Assignee: Micron Technology, Inc.Inventors: Yantao Ma, Aaron Willey
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Patent number: 9202542Abstract: Examples of circuits and methods for compensating for power supply induced signal jitter in path elements sensitive to power supply variation. An example includes a signal path coupling an input to an output, the signal path including a delay element having a first delay and a bias-controlled delay element having a second delay. The first delay of the delay element exhibits a first response to changes in power applied thereto and the second delay of the bias-controlled delay element exhibits a second response to changes in the power applied such that the second response compensates at least in part for the first response.Type: GrantFiled: July 14, 2014Date of Patent: December 1, 2015Assignee: Micron Technology, Inc.Inventors: Yantao Ma, Aaron Willey
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Patent number: 9036408Abstract: Methods, circuits, and systems for phase change memories. A matching bit line, on which no data-containing PCM cells have been selected, is used to cancel out time-dependent current components due to parasitic capacitive and leakage resistance loading of bit lines. This can effectively allow direct comparison of the current from the phase change memory cell to the desired reference current, at a time before the voltage of the first bit line permits stable operations using DC comparison.Type: GrantFiled: August 27, 2013Date of Patent: May 19, 2015Inventors: Ryan Jurasek, Aaron Willey
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Patent number: 8947141Abstract: A differential amplifier may be configured to have a duty cycle and/or gain that is adjustable, such as by adjusting the switch points of circuitry in the differential amplifier. The differential amplifier may alternatively or additionally have a hysteresis function by, for example, using a signal feedback from the output of the amplifier to adjust the switch points of circuitry in the differential amplifier. The differential amplifier may be used for a variety of purposes, such as in an input buffer or delay line, either of which may be used, for example, in a clock generator circuit.Type: GrantFiled: May 19, 2014Date of Patent: February 3, 2015Assignee: Micron Technology, Inc.Inventor: Aaron Willey
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Publication number: 20140375366Abstract: Measurement initialization circuitry is described. Propagation of a start signal through a variable delay line may be stopped by either of two stop signals. One stop signal corresponds to a rising edge of a reference clock signal. A second stop signal corresponds to a falling edge of the reference clock signal. The start signal propagation is stopped responsive to the first to arrive of the first and second stop signals. Accordingly, in some examples, start signal propagation through a variable delay line may be stopped responsive to either a rising or falling edge of the reference clock signal.Type: ApplicationFiled: September 10, 2014Publication date: December 25, 2014Inventors: Aaron Willey, Yantao Ma
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Patent number: 8901938Abstract: A measure initialization path for a delay line structure includes: a forward path, comprising a plurality of delay stages coupled in series; a first output path coupled to at least an output of a delay stage of the forward path, where at least an output of a delay stage is fed forward to the forward path; and a second output path coupled to at least an output of a delay stage of the forward path, where at least an output of a delay stage is fed forward to the forward path. When a signal is propagated through the measure initialization path, the signal successively propagates through a delay stage of the forward path, a delay stage of the first output path and a delay stage of the second output path for performing measure initialization.Type: GrantFiled: February 1, 2012Date of Patent: December 2, 2014Assignee: Nanya Technology Corp.Inventors: Aaron Willey, Yantao Ma
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Publication number: 20140340069Abstract: Current circuits, circuits configured to provide a bias voltage, and methods for providing a bias voltage are described, including a current circuit configured to receive a reference current and having an output at which an output current is provided. One such current circuit includes a first current mirror configured to receive a first portion of the reference current and further configured to mirror the first portion of the reference current to provide a first current. The current circuit further includes a second current mirror configured to receive a second portion of the reference current and receive the first current. The second current mirror is further configured to provide a portion of the first current to the output of the current circuit as the output current and to receive another portion of the first current and mirror the same as the second portion of the reference current.Type: ApplicationFiled: July 31, 2014Publication date: November 20, 2014Inventor: AARON WILLEY
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Publication number: 20140320190Abstract: Examples of circuits and methods for compensating for power supply induced signal jitter in path elements sensitive to power supply variation. An example includes a signal path coupling an input to an output, the signal path including a delay element having a first delay and a bias-controlled delay element having a second delay. The first delay of the delay element exhibits a first response to changes in power applied thereto and the second delay of the bias-controlled delay element exhibits a second response to changes in the power applied such that the second response compensates at least in part for the first response.Type: ApplicationFiled: July 14, 2014Publication date: October 30, 2014Inventors: Yantao Ma, Aaron Willey
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Patent number: 8841949Abstract: Measurement initialization circuitry is described. Propagation of a start signal through a variable delay line may be stopped by either of two stop signals. One stop signal corresponds to a rising edge of a reference clock signal. A second stop signal corresponds to a falling edge of the reference clock signal. The start signal propagation is stopped responsive to the first to arrive of the first and second stop signals. Accordingly, in some examples, start signal propagation through a variable delay line may be stopped responsive to either a rising or falling edge of the reference clock signal.Type: GrantFiled: December 10, 2013Date of Patent: September 23, 2014Assignee: Micron Technology, Inc.Inventors: Aaron Willey, Yantao Ma
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Publication number: 20140253193Abstract: A differential amplifier may be configured to have a duty cycle and/or gain that is adjustable, such as by adjusting the switch points of circuitry in the differential amplifier. The differential amplifier may alternatively or additionally have a hysteresis function by, for example, using a signal feedback from the output of the amplifier to adjust the switch points of circuitry in the differential amplifier. The differential amplifier may be used for a variety of purposes, such as in an input buffer or delay line, either of which may be used, for example, in a clock generator circuit.Type: ApplicationFiled: May 19, 2014Publication date: September 11, 2014Applicant: Micron Technology, Inc.Inventor: Aaron Willey
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Patent number: 8829882Abstract: Current circuits, circuits configured to provide a bias voltage, and methods for providing a bias voltage are described, including a current circuit configured to receive a reference current and having an output at which an output current is provided. One such current circuit includes a first current mirror configured to receive a first portion of the reference current and further configured to mirror the first portion of the reference current to provide a first current. The current circuit further includes a second current mirror configured to receive a second portion of the reference current and receive the first current. The second current mirror is further configured to provide a portion of the first current to the output of the current circuit as the output current and to receive another portion of the first current and mirror the same as the second portion of the reference current.Type: GrantFiled: August 31, 2010Date of Patent: September 9, 2014Assignee: Micron Technology, Inc.Inventor: Aaron Willey