Patents by Inventor Aarti Gupta

Aarti Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150081243
    Abstract: Disclosed are a testing framework—SETSUD ?—that uses perturbation-based exploration for robustness testing of modern scalable distributed systems. In sharp contrast to existing testing techniques and tools that are limited in that they are typically based on black-box approaches or they focus mostly on failure recovery testing, SETSUD ? is a flexible framework to exercise various perturbations to create stressful scenarios. SETSUD ? is built on an underlying instrumentation infrastructure that provides abstractions of internal states of the system as labeled entities. Both novice and advanced testers can use these labeled entities to specify scenarios of interest at the high level, in the form of a declarative style test policy. SETSUD ? automatically generates perturbation sequences and applies them to system-level implementations, without burdening the tester with low-level details.
    Type: Application
    Filed: March 18, 2014
    Publication date: March 19, 2015
    Applicant: NEC Laboratories America, Inc.
    Inventors: Malay Ganai, Gogul Balakrishnan, Pallavi Joshi, Aarti Gupta
  • Publication number: 20140337674
    Abstract: A network testing method implemented in a software-defined network (SDN) is disclosed. The network testing method comprising providing a test scenario including one or more network events, injecting said one or more network events to the SDN using an SDN controller, and gathering network traffic statistics. A network testing apparatus used in a software-defined network (SDN) also is disclosed. The network testing apparatus comprising a testing system to provide a test scenario including one or more network events, to inject said one or more network events to the SDN using an SDN controller, and to gather network traffic statistics. Other methods, apparatuses, and systems also are disclosed.
    Type: Application
    Filed: May 6, 2014
    Publication date: November 13, 2014
    Applicant: NEC Laboratories America, Inc.
    Inventors: Franjo Ivancic, Cristian Lumezanu, Gogul Balakrishnan, Willard Dennis, Aarti Gupta
  • Publication number: 20140289712
    Abstract: Disclosed are typestate and lifetime dependency analysis methods for identifying bugs in C++ programs. Disclosed are an abstract representation (ARC++) that models C++ objects and which makes object creation/destruction, usage, lifetime and pointer operations explicit in the abstract model thereby providing a basis for static analysis on the C++ program. Also disclosed is a lifetime dependency analysis that tracks implied dependency relationships between lifetimes of objects, to capture an effective high-level abstraction for issues involving temporary objects and internal buffers, and subsequently used in the static analysis that supports typestate checking for the C++ program. Finally disclosed a framework that automatically genarates ARC++ representations from C++ programs and performs typestate checking to detect bugs that are specified as typestate automata over ARC++ representations.
    Type: Application
    Filed: March 6, 2014
    Publication date: September 25, 2014
    Applicant: NEC Laboratories America, Inc.
    Inventors: Aarti Gupta, Gogul Balakrishnan, Franjo Ivancic, Xusheng Xiao
  • Patent number: 8799194
    Abstract: Systems and methods for model checking of live systems are shown that include learning an interval discrete-time Markov chain (IDTMC) model of a deployed system from system logs; and checking the IDTMC model with a processor to determine a probability of violating one or more probabilistic safety properties. Checking the IDTMC model includes calculating a linear part exactly using affine arithmetic; and over-approximating a non-linear part using interval arithmetic.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: August 5, 2014
    Assignee: NEC Laboratories America, Inc.
    Inventors: Parasara Sridhar Duggirala, Khalil Ghorbal, Franjo Ivancic, Vineet Kahlon, Aarti Gupta
  • Patent number: 8719802
    Abstract: An interprocedural exception analysis and transformation framework for computer programming languages such as C++ that (1) captures the control-flow induced by exceptions precisely, and (2) transforms the given computer program into an exception-free program that is amenable for precise static analysis, verification, and optimizations.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: May 6, 2014
    Assignees: NEC Laboratories America, Inc., NEC Corporation
    Inventors: Naoto Maeda, Prakash Prabhu, Gogul Balakrishnan, Franjo Ivancic, Aarti Gupta
  • Patent number: 8719793
    Abstract: A scalable, computer implemented method for finding subtle flaws in software programs. The method advantageously employs 1) scope bounding which limits the size of a generated model by excluding deeply-nested function calls, where the scope bounding vector is chosen non-monotonically, and 2) automatic specification inference which generates constraints for functions through the effect of a light-weight and scalable global analysis. Advantageously, scalable software model checking is achieved while at the same time finding more bugs.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: May 6, 2014
    Assignees: NEC Laboratories America, Inc., NEC Corporation
    Inventors: Naoto Maeda, Franjo Ivancic, Sriram Sankaranarayanan, Aarti Gupta
  • Patent number: 8707278
    Abstract: A model is provided for transforming a program with a priori given class hierarchy that is induced by inheritance. An inheritance remover is configured to remove inheritance from a given program to produce an analysis-friendly program which does not include virtual-function pointer tables and runtime libraries associated with inheritance-related operations. The analysis-friendly program preserves the semantics of the given program with respect to a given class hierarchy. A clarifier is configured to identify implicit expressions and function calls and transform the given program into at least one intermediate program having explicit expressions and function calls.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: April 22, 2014
    Assignee: NEC Laboratories America, Inc.
    Inventors: Gogul Balakrishnan, Naoto Maeda, Franjo Ivancic, Nishant Sinha, Aarti Gupta, Jing Yang
  • Publication number: 20140108867
    Abstract: Disclosed is a dynamic taint analysis framework for multithreaded programs (DTAM) that identifies a subset of program inputs and shared memory accesses that are relevant for issues related to concurrency. Computer implemented methods according to the framework generally involve the computer implemented steps of: applying independently a dynamic taint analysis to each of the multiple threads comprising a multi-threaded computer program; aggregating each independent result from the analysis for each of the multiple threads by consolidating effect of taint analysis in one or more possible re-orderings of observed shared memory accesses among threads; and outputting an indicia of the aggregated result as a set of relevant program inputs or a set of relevant shared memory accesses.
    Type: Application
    Filed: March 13, 2013
    Publication date: April 17, 2014
    Applicant: NEC LABORATORIES AMERICA, INC.
    Inventors: Malay Ganai, Dongyoon Lee, Aarti Gupta
  • Publication number: 20130332906
    Abstract: A method to test a concurrent program by performing a concolic multi-trace analysis (CMTA) to analyze the concurrent program by taking two or more test runs over many threads and generating a satisfiability modulo theory (SMT) formula to select alternate inputs, alternate schedules and parts of threads from one or more test runs; using an SMT solver on the SMT formula for generating a new concurrent test comprising input values, thread schedules and parts of thread selections; and executing the new concurrent test.
    Type: Application
    Filed: May 1, 2013
    Publication date: December 12, 2013
    Inventors: Niloofar Razavi, Franjo Ivancic, Vineet Kahlon, Aarti Gupta
  • Patent number: 8601459
    Abstract: A system and method for discovering a set of possible iteration sequences for a given loop in a software program is described, to transform the loop representation. In a program containing a loop, the loop is partitioned into a plurality of portions based on splitting criteria. Labels are associated with the portions, and an initial loop automaton is constructed that represents the loop iterations as a regular language over the labels corresponding to the portions in the program. Subsequences of the labels are analyzed to determine infeasibility of the subsequences permitted in the automaton. The automaton is refined by removing all infeasible subsequences to discover a set of possible iteration sequences in the loop. The resulting loop automaton is used in a subsequent program verification or analysis technique to find violations of correctness properties in programs.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: December 3, 2013
    Assignee: NEC Laboratories America, Inc.
    Inventors: Sriram Sankaranarayanan, Aarti Gupta, Gogul Balakrishnan
  • Patent number: 8538900
    Abstract: A system and method for deciding the satisfiability of a non-linear real decision problem is disclosed. Linear and non-linear constraints associated with the problem are separated. The feasibility of the linear constraints is determined using a linear solver. The feasibility of the non-linear constraints is determined using a non-linear solver which employs interval constraint propagation. The interval solutions obtained from the non-linear solver are validated using the linear solver. If the solutions cannot be validated, linear constraints are learned to refine a search space associated with the problem. The learned constraints and the non-linear constraints are iteratively solved using the non-linear solver until either a feasible solution is obtained or no solution is possible.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: September 17, 2013
    Assignee: NEC Laboratories America, Inc.
    Inventors: Malay K. Ganai, Sicun Gao, Franjo Ivancic, Aarti Gupta
  • Patent number: 8539451
    Abstract: Methods and systems for verifying the precision of a program that utilizes floating point operations are disclosed. Interval and affine arithmetic can be employed to build a model of the program including floating point operations and variables that are expressed as reals and integers, thereby permitting accurate determination of precision loss using a model checker. Abstract interpretation can be also employed to simplify the model. In addition, counterexample-guided abstraction refinement can be used to refine the values of parametric error constants introduced in the model.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: September 17, 2013
    Assignee: NEC Laboratories America, Inc.
    Inventors: Franjo Ivancic, Malay K. Ganai, Sriram Sankaranarayanan, Aarti Gupta
  • Patent number: 8527976
    Abstract: A system and method for program verification includes generating a product transaction graph for a concurrent program, which captures warnings for potential errors. The warnings are filtered to remove bogus warnings, by using constraints from synchronization primitives and invariants that are derived by performing one or more dataflow analysis methods for concurrent programs. The dataflow analysis methods are applied in order of overhead expense. Concrete execution traces are generated for remaining warnings using model checking.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: September 3, 2013
    Assignee: NEC Laboratories America, Inc.
    Inventors: Vineet Kahlon, Sriram Sankarnarayanan, Aarti Gupta
  • Patent number: 8522226
    Abstract: A system and method for discovering a set of possible iteration sequences for a given loop in a software program is described, to transform the loop representation. In a program containing a loop, the loop is partitioned into a plurality of portions based on splitting criteria. Labels are associated with the portions, and an initial loop automaton is constructed that represents the loop iterations as a regular language over the labels corresponding to the portions in the program. Subsequences of the labels are analyzed to determine infeasibility of the subsequences permitted in the automaton. The automaton is refined by removing all infeasible subsequences to discover a set of possible iteration sequences in the loop. The resulting loop automaton is used in a subsequent program verification or analysis technique to find violations of correctness properties in programs.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: August 27, 2013
    Assignee: NEC Laboratories America, Inc.
    Inventors: Sriram Sankaranarayanan, Aarti Gupta, Gogul Balakrishnan
  • Patent number: 8402440
    Abstract: Systems and methods are disclosed to verify a program by symbolically enumerating path programs; verifying each path program to determine if the path program is correct or leads to a violation of a correctness property; determining a conflict set from the path program if the path program is proved correct; using the conflict set to avoid enumerating other related path programs that are also correct.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: March 19, 2013
    Assignee: NEC Laboratories America, Inc.
    Inventors: Sriram Sankaranarayanan, Franjo Ivancic, William R Harris, Aarti Gupta, Gogul Balakrishnan
  • Patent number: 8381226
    Abstract: A system and method for analyzing concurrent programs that guarantees optimality in the number of thread inter-leavings to be explored. Optimality is ensured by globally constraining the inter-leavings of the local operations of its threads so that only quasi-monotonic sequences of threads operations are explored. For efficiency, a SAT/SMT solver is used to explore the quasi-monotonic computations of the given concurrent program. Constraints are added dynamically during exploration of the concurrent program via a SAT/SMT solver to ensure quasi-montonicity for model checking.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: February 19, 2013
    Assignee: NEC Laboratories America, Inc.
    Inventors: Vineet Kahlon, Chao Wang, Aarti Gupta
  • Patent number: 8374840
    Abstract: A system and method for generating test vectors includes generating traces of a system model or program stored in memory using a simulation engine. Simulated inputs are globally optimized using a fitness objective computed using a computer processing device. The simulation inputs are adjusted in accordance with feedback from the traces and fitness objective values by computing a distance between the fitness objective value and a reachability objective. Test input vectors are output based upon optimized fitness objective values associated with the simulated inputs to test the system model or program stored in memory.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: February 12, 2013
    Assignee: NEC Laboratories America, Inc.
    Inventors: Sriram Sankaranarayanan, Franjo Ivancic, Aarti Gupta, Truong X. Nghiem
  • Patent number: 8365152
    Abstract: A system and method for infeasible path detection includes performing a static analysis on a program to prove a property of the program. If the property is not proved, infeasible paths in the program are determined by performing a path-insensitive abstract interpretation. Information about such infeasible paths is used to achieve the effects of path-sensitivity in path-insensitive program analysis.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: January 29, 2013
    Assignee: NEC Laboratories America, Inc.
    Inventors: Gogul Balakrishnan, Sriram Sankaranarayanan, Franjo Ivancic, Aarti Gupta
  • Patent number: 8359578
    Abstract: A computer implemented method for the verification of concurrent software programs wherein the concurrent software program is partitioned into subsets named concurrent trace programs (CTPs) and each of the CTPs is evaluated using a satisfiability-based (SAT) symbolic analysis. By applying the SAT analysis to individual CTPs in isolation the symbolic analysis is advantageously more scalable and efficient.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: January 22, 2013
    Assignee: NEC Laboratories America, Inc.
    Inventors: Chao Wang, Aarti Gupta, Swarat Chaudhuri, Yu Yang
  • Patent number: 8286137
    Abstract: A system and method for program verification by model checking in concurrent programs includes modeling each of a plurality of program threads as a circuit model, and generating a full circuit for an entire program by combining the circuit models including constraints which enforce synchronous execution of the program threads. The program is verified using the synchronous execution to reduce an amount of memory needed to verify the program and a number of steps taken to uncover an error.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: October 9, 2012
    Assignee: NEC Laboratories America, Inc.
    Inventors: Vineet Kahlon, Aarti Gupta