Patents by Inventor Aarul Jain
Aarul Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12164369Abstract: A system-on-chip (SoC) may include a plurality of terminals and a plurality of terminal controllers. Each terminal controller is configured to selectively disable a terminal. An SoC be configured to execute at least one application. An SoC may include a memory configured to store a plurality of terminal masks. Each terminal mask identifies a subset of the plurality of terminals to be disabled. An SoC may include a fault collection and reaction system configured to transmit, to the plurality of terminal controllers, a fault indication signal in response to an error in a corresponding application. Each terminal controller is further configured to determine, based on a fault indication signal and a value in a terminal mask, whether the terminal corresponding to the terminal controller is to be disabled, and when the terminal corresponding to the terminal controller is to be disabled, disable the terminal.Type: GrantFiled: January 10, 2023Date of Patent: December 10, 2024Assignee: NXP B.V.Inventors: Ankush Sethi, Rohit Kumar Kaul, Aarul Jain
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Publication number: 20240354187Abstract: A fault indication from a fault source is to be provided to a demultiplexer which is configured to output the fault indication. The demultiplexer is configurable to output the fault indication to an OR gate of a plurality of OR gates coupled to a respective fault channel of a plurality of fault channels based on an application which uses the fault source as a resource. A reaction to the fault indication is performed based on the fault channel which received the fault indication.Type: ApplicationFiled: June 15, 2023Publication date: October 24, 2024Inventors: Aarul Jain, Hemant Nautiyal, Ashu Gupta
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Publication number: 20240143429Abstract: A system-on-chip (SoC) may include a plurality of terminals and a plurality of terminal controllers. Each terminal controller is configured to selectively disable a terminal. An SoC be configured to execute at least one application. An SoC may include a memory configured to store a plurality of terminal masks. Each terminal mask identifies a subset of the plurality of terminals to be disabled. An SoC may include a fault collection and reaction system configured to transmit, to the plurality of terminal controllers, a fault indication signal in response to an error in a corresponding application. Each terminal controller is further configured to determine, based on a fault indication signal and a value in a terminal mask, whether the terminal corresponding to the terminal controller is to be disabled, and when the terminal corresponding to the terminal controller is to be disabled, disable the terminal.Type: ApplicationFiled: January 10, 2023Publication date: May 2, 2024Inventors: Ankush SETHI, Rohit Kumar KAUL, Aarul JAIN
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Publication number: 20230417888Abstract: An object detection system that includes a transceiver and processing circuitry is disclosed. The transceiver receives a chirp wave reflected from a real object that is in the vicinity of the object detection system, and generates echo data based on the received chirp wave. The processing circuitry generates detection data that includes the echo data and target data associated with a virtual object. The target data is generated to identify a fault in the object detection system while the object detection system is operating in-field. Further, the target data is indicative of predefined parameters of the virtual object. The processing circuitry then processes the detection data to detect the virtual object and extract various parameters of the detected virtual object. Further, the processing circuitry identifies the fault in the object detection system based on a comparison of the extracted parameters with the predefined parameters.Type: ApplicationFiled: August 16, 2022Publication date: December 28, 2023Inventors: Aditya Khandelwal, Aarul Jain, Rupesh Chaturvedi
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Patent number: 11853157Abstract: An address fault detection system includes write and read access circuits and a fault management circuit. The write access circuit receives an address and reference data for a write operation associated with a memory and parity data generated based on the reference data, and writes the reference data and the parity data to first and second memory blocks of the memory, respectively. The read access circuit receives the same address for a read operation associated with the memory and reads another reference data and another parity data from the first and second memory blocks, respectively. The fault management circuit compares the read parity data with parity data generated based on the read reference data to detect an address fault in the memory. The written and read reference data are different when the address fault is detected, and same when the address fault is not detected.Type: GrantFiled: November 17, 2021Date of Patent: December 26, 2023Assignee: NXP B.V.Inventors: Arvind Kaushik, Aarul Jain, Nishant Jain
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Publication number: 20230153197Abstract: An address fault detection system includes write and read access circuits and a fault management circuit. The write access circuit receives an address and reference data for a write operation associated with a memory and parity data generated based on the reference data, and writes the reference data and the parity data to first and second memory blocks of the memory, respectively. The read access circuit receives the same address for a read operation associated with the memory and reads another reference data and another parity data from the first and second memory blocks, respectively. The fault management circuit compares the read parity data with parity data generated based on the read reference data to detect an address fault in the memory. The written and read reference data are different when the address fault is detected, and same when the address fault is not detected.Type: ApplicationFiled: November 17, 2021Publication date: May 18, 2023Inventors: Arvind Kaushik, Aarul Jain, Nishant Jain
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Patent number: 9727408Abstract: An error detection system detects errors in data packets stored in a memory. A read signature generation circuit generates a read signature of a first data packet. A write signature generation circuit generates a write signature of a second data packet. When a trigger generation circuit generates a trigger signal, a first latching circuit stores a write address as a latch write address and a second latch stores the write signature as a latch write signature. A first synchronization and comparison circuit generates a comparison signal based on the latched write address and a read address. A second synchronization and comparison circuit generates a fault signal based on the comparison signal, the latched write signature, and the read signature.Type: GrantFiled: December 20, 2015Date of Patent: August 8, 2017Assignee: NXP USA, INC.Inventors: Aarul Jain, Dirk Wendel
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Publication number: 20170177428Abstract: An error detection system detects errors in data packets stored in a memory. A read signature generation circuit generates a read signature of a first data packet. A write signature generation circuit generates a write signature of a second data packet. When a trigger generation circuit generates a trigger signal, a first latching circuit stores a write address as a latch write address and a second latch stores the write signature as a latch write signature. A first synchronization and comparison circuit generates a comparison signal based on the latched write address and a read address. A second synchronization and comparison circuit generates a fault signal based on the comparison signal, the latched write signature, and the read signature.Type: ApplicationFiled: December 20, 2015Publication date: June 22, 2017Inventors: Aarul Jain, Dirk Wendel
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Patent number: 9251906Abstract: A method and circuit for generating a shifted strobe signal for sampling data read from a memory device includes generating an instantiation of a shifted strobe signal by applying both a coarse adjustment delay value and a fine adjustment delay value to a clock. Data read from a predetermined, programmed memory location or locations of the memory device is sampled using the shifted strobe signal. At least one of the applying steps is repeated and the read data is sampled again using the current instantiation of the shifted strobe signal. The process is repeated until the current instantiation of the shifted strobe signal is aligned with a valid data window of the memory device. The method can be used in both single data rate and double data rate applications.Type: GrantFiled: May 18, 2015Date of Patent: February 2, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Aarul Jain, Neha Agarwal, Rakesh Pandey, Deboleena Minz Sakalley
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Patent number: 9129661Abstract: A single-port memory that operates in single-cycle dual-port mode has a logical capacity of N=k·m memory words and (k+1) single-port RAM having an overall physical capacity of (k+1)·m memory words. A status register holds words identifying which RAM bank has the last data at the ith address in the RAM banks and defining k status words for valid data among the (k+1) RAM banks. Write data is written to the write address of a valid RAM bank for a write operation in the absence of RAM bank read address contention. Write data is written to the write address of a different RAM bank that has no valid data for a write operation if there is contention with the RAM bank read address RADDR of a read operation. The status register is updated to identify the RAM bank of the write operation.Type: GrantFiled: September 1, 2013Date of Patent: September 8, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Aarul Jain, Rakesh Pandey, Rohit S. Patel
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Publication number: 20150067275Abstract: A single-port memory that operates in single-cycle dual-port mode has a logical capacity of N=k·m memory words and (k+1) single-port RAM having an overall physical capacity of (k+1)·m memory words. A status register holds words identifying which RAM bank has the last data at the ith address in the RAM banks and defining k status words for valid data among the (k+1) RAM banks. Write data is written to the write address of a valid RAM bank for a write operation in the absence of RAM bank read address contention. Write data is written to the write address of a different RAM bank that has no valid data for a write operation if there is contention with the RAM bank read address RADDR of a read operation. The status register is updated to identify the RAM bank of the write operation.Type: ApplicationFiled: September 1, 2013Publication date: March 5, 2015Inventors: Aarul Jain, Rakesh Pandey, Rohit S. Patel