Patents by Inventor Aashish Phansalkar

Aashish Phansalkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Instruction boundary prediction for variable length instruction set
    Patent number: 9223714
    Abstract: A system, processor, and method to predict with high accuracy and retain instruction boundaries for previously executed instructions in order to decode variable length instructions is disclosed. In at least one embodiment, a disclosed processor includes an instruction fetch unit, an instruction cache, a boundary byte predictor, and an instruction decoder. In some embodiments, the instruction fetch unit provides an instruction address and the instruction cache produces an instruction tag and instruction cache content corresponding to the instruction address. The instruction decoder, in some embodiments, includes boundary byte logic to determine an instruction boundary in the instruction cache content.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 29, 2015
    Assignee: Intel Corporation
    Inventors: Mauricio Breternitz, Youfeng Wu, Peter Sassone, James Mason, Aashish Phansalkar, Balaji Vijayan
  • INSTRUCTION BOUNDARY PREDICTION FOR VARIABLE LENGTH INSTRUCTION SET
    Publication number: 20140281246
    Abstract: A system, processor, and method to predict with high accuracy and retain instruction boundaries for previously executed instructions in order to decode variable length instructions is disclosed. In at least one embodiment, a disclosed processor includes an instruction fetch unit, an instruction cache, a boundary byte predictor, and an instruction decoder. In some embodiments, the instruction fetch unit provides an instruction address and the instruction cache produces an instruction tag and instruction cache content corresponding to the instruction address. The instruction decoder, in some embodiments, includes boundary byte logic to determine an instruction boundary in the instruction cache content.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Mauricio Breternitz, JR., Youfeng Wu, Peter Sassone, James Mason, Aashish Phansalkar, Balaji Vijayan